Body-Biased Voltage-to-Time Converter for Rail-to-Rail Linearity
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Solution Overview
Problem
Conventional voltage-domain analog-to-digital converters (ADCs) face challenges with signal-to-noise ratio attenuation, nonlinearity, and limited dynamic range due to scaling in semiconductor processes, while time-domain ADCs struggle with non-ideal factors affecting voltage-to-time converter (VTC) performance, particularly in achieving rail-to-rail input range and linear voltage delay response.
Innovation Solution
A voltage-to-time converter design combining current starving, current mirror, and body biasing technologies, utilizing PMOS and NMOS transistors with specific connections and body bias inputs to achieve a highly linear and wide rail-to-rail dynamic input range, where the input voltage is used as the body bias voltage to control the drain current of transistors, ensuring linear voltage delay response and expanded input range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If current starving technology and current mirror technology are used to extend the linear range of VTC, then the dynamic input range is improved, but the circuit still cannot achieve rail-to-rail dynamic input range due to the quadratic relationship between drain current and gate-source voltage
Solution Approach 1:
The patent changes the control parameter from gate-source voltage to body bias voltage. By applying body bias to the current mirror transistors, the drain current becomes linearly proportional to the body bias voltage, eliminating the quadratic nonlinearity inherent in gate-source voltage control. This parameter change enables both extended dynamic range and maintained linearity simultaneously.
2Device complexity
If the input voltage is used as the supply voltage of the standard inverter to implement V/T conversion, then the circuit structure is simplified, but the linear input range is limited to only 200 mV
Solution Approach 1:
The patent makes the body bias voltage serve multiple functions: it controls the drain current of the current mirror transistors to achieve linear voltage-to-time conversion, and simultaneously extends the input voltage range to rail-to-rail. This multi-functionality resolves the contradiction between circuit simplicity and input range extension.
3Use of energy by stationary object
If nanometer-sized transistors are continuously scaled and power supply voltage is decreased, then the power consumption is reduced, but the signal-to-noise ratio and linearity are attenuated due to non-ideal factors
Solution Approach 1:
The patent replaces the conventional voltage-domain ADC approach with a time-domain ADC architecture. By converting the input voltage to a time delay signal and then to digital code, the system avoids the SNR degradation issues inherent in voltage-domain processing at low supply voltages, while maintaining low power consumption through efficient time-domain operation.
Data Source
AI summary
A voltage-to-time converter (VTC) for a time-domain analog-to-digital converter is disclosed, which provides a time-domain analog-to-digital converter (T-ADC) with low power consumption and high precision. By combining the advantages of current-starving technology, current mirror technology, and body biasing technology, compared with the traditional structure, the VTC and T-ADC achieve excellent performance, such as low power consumption, high linearity, wide input dynamic range, and strong anti-interference to PVT variations. Compared with the traditional voltage-to-time converter, the disclosed voltage-to-time converter has a wider input dynamic range and higher linearity. The input voltage is connected to transistors in the circuit as a body bias, resulting in a very small body current, and no apparent increase in power consumption. The design of a low-power voltage-to-time converter is realized.