Power FET Built-In Self-Test Circuit for Parasitic-Free Measurement
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Solution Overview
Problem
Current methods for testing power field effect transistors (FETs) on semiconductor substrates face issues such as the addition of parasitic resistance and particle transfer due to the use of probe needles in automated test equipment, and the large area coverage of power FETs poses challenges in effective testing.
Innovation Solution
A built-in self-test circuit is implemented on the substrate, utilizing a switch controller and analog-to-digital converter to alternately turn on and off FETs, measuring the source-drain resistance by digitizing voltage drops and comparing them to predefined ranges, with a logical OR-gate indicating any defective channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If probe needles are used in automated test equipment to measure drain-source resistance of power FETs, then testing can be performed externally, but parasitic resistance is added and particles are transferred between wafers
Solution Approach 1:
The power FETs test each other using built-in test circuits on the same substrate. The first power device serves as the test object while the second power device acts as the test instrument, eliminating the need for external probe needles and their associated parasitic resistance and contamination issues.
Solution Approach 2:
A built-in test current source and voltage measurement circuit serve as intermediaries between the power FETs under test and the external testing system. These intermediaries are integrated on the substrate and eliminate direct contact with external probe needles, thereby avoiding parasitic resistance and particle transfer.
2Power
If power FETs cover up to seventy five percent of the semiconductor area, then high power capability is achieved, but testing becomes more challenging due to large area coverage
Solution Approach 1:
The substrate is divided into multiple independent test units, each containing power FETs that can be tested individually. The switch controller selectively activates specific FETs for testing, allowing systematic testing of large-area substrates by breaking down the complex testing task into manageable segments.
Solution Approach 2:
The switch controller periodically activates different power FETs for testing in a sequential manner. By cycling through different FETs and their corresponding test circuits, the system can comprehensively test all power devices on the substrate over time, managing the complexity of testing large-area coverage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method allows for accurate and parasitic resistance-free testing of power FETs, avoiding the need for external test equipment and ensuring the detection of defective regions without contaminating the substrate.
Implementation Method 1
an analog to digital converter (ADC) coupled to the first common junction and the second common junction and configured to alternately digitize a voltage of the first channel region or the second channel region
Data Source
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AI summary
A circuit includes first and second power devices that include first and second field effect transistors (FET). A first channel is located between a first drain and a first source of first FET and a second channel is located between a second drain and a second source of second FET. First and second drains are coupled to first common junction and first and second sources are coupled to second common junction. The first common junction is configured to receive a current. A switch controller is coupled to a first gate of the first FET and to a second gate of the second FET to apply a bias voltage to the first and second gates one by one and in turn. An analog to digital converter coupled to first common junction and second common junction and configured to alternately digitize a voltage of the first channel or the second channel.