On-Chip ADC Self-Calibration for Interleave Error Correction
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Solution Overview
Problem
Existing Analog-to-Digital Converter (ADC) calibration methods require expensive and elaborate external setups, leading to high costs and inefficiencies due to manufacturing process variations causing interleave errors that degrade Signal-to-Noise Ratio (SNR).
Innovation Solution
An on-chip circuit with a calibration source and switches allows for self-calibration by disconnecting the in-service signal during calibration mode, using either synchronous or asynchronous signals, and employing a calibration algorithm to determine and correct interleave errors, eliminating the need for external equipment and human intervention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If external calibration setup with synthesizers and power splitters is used, then ADC calibration accuracy is improved, but device complexity and cost increase
Solution Approach 1:
The patent extracts the calibration source functionality from external equipment and integrates it directly into the ADC chip. The calibration source is implemented as an on-chip circuit that generates calibration signals internally, eliminating the need for external synthesizers, power splitters, and other calibration equipment. This extraction principle resolves the contradiction by maintaining calibration accuracy while dramatically reducing setup complexity.
Solution Approach 2:
The ADC performs calibration using its own internal resources - the on-chip calibration source generates test signals, the ADC channels process them, and the system automatically computes correction factors. This self-service approach eliminates human intervention and external equipment, resolving the contradiction between calibration accuracy and device complexity by making the ADC autonomous in its calibration process.
2Measurement precision
If external calibration equipment and human intervention are used, then calibration accuracy is improved, but productivity decreases
Solution Approach 1:
The ADC system performs calibration autonomously using on-chip resources. The calibration source generates signals, the ADC channels process them, and the system automatically computes correction factors without human intervention. This self-service mechanism resolves the contradiction by maintaining calibration accuracy while dramatically improving productivity through automated, rapid calibration cycles.
Solution Approach 2:
The calibration functionality is built into the ADC chip design itself, with calibration sources and control circuits integrated beforehand. This preliminary preparation allows the ADC to perform calibration quickly and automatically when needed, resolving the contradiction by having calibration capability ready in advance rather than requiring external setup at calibration time.
3Device complexity
If on-chip calibration circuit is used, then device complexity is reduced, but measurement precision may worsen
Solution Approach 1:
The patent extracts the essential calibration signal generation function and places it on-chip, while maintaining the ADC's existing high-precision architecture. The on-chip calibration source is designed to generate accurate test signals that properly stress the ADC channels, ensuring that calibration measurements remain precise despite the simplified on-chip implementation.
Solution Approach 2:
The calibration source is designed with specific local characteristics optimized for calibration purposes - generating signals at frequencies and amplitudes specifically suited for measuring ADC channel mismatches. This localized optimization ensures that despite the simplified on-chip implementation, the calibration measurements maintain high precision by using signal characteristics specifically tailored for the measurement task.
Data Source
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AI summary
An Analog-to-Digital Converter, ADC, (5) includes a plurality of ADC channels (12, 14) connected to an in-service signal input (16) via an isolated power combiner (18); an on-chip circuit (10) including a calibration source (20) connected to the isolated power combiner (18); and one or more switches (28, 32) configured to switch the ADC (5) between an in-service mode and a calibration mode. The one or more switches (28, 32) are set such that, in the calibration mode, the in-service signal input (16) is disconnected and the on-chip circuit (10) is connected to the isolated power combiner (18), and, in the in- service mode, the in-service signal input (16) is connected and the on-chip circuit (10) is disconnected to the isolated power combiner (18). In the calibration mode, the on-chip circuit (10) is configured to provide a test signal to the plurality of ADC channels (12, 14) for a determination of interleave errors in the plurality of ADC channels (12, 14).