CT ADC Sub-DAC Error Correction for Low Noise and Distortion
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Solution Overview
Problem
Conventional approaches to addressing sub-DAC mismatch errors in continuous-time analog-to-digital converters (ADCs) face challenges such as increased noise spectral density, distortion, and complexity, particularly in high-speed applications, where achieving low noise spectral density and low distortion simultaneously is difficult.
Innovation Solution
The proposed solution involves estimating and digitally correcting sub-DAC errors ahead of time, using mechanisms that allow for the reduction or elimination of errors in the digital domain, specifically through error extraction and correction methods such as foreground and background extraction approaches, which can be implemented in both continuous-time and hybrid ADCs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional approaches are used to address sub-DAC mismatch errors, then device complexity increases, but noise spectral density and distortion performance deteriorate
Solution Approach 1:
The patent replaces conventional analog correction circuits with a digital correction approach. Error correction is performed in the digital domain using a correction code generated from the digital output of the ADC, eliminating the need for complex analog correction hardware while achieving superior noise and distortion performance.
Solution Approach 2:
The patent introduces an intermediary error correction code that mediates between the sub-DAC output and the final ADC output. This correction code, generated through digital processing of the ADC output, serves as a mediator to compensate for sub-DAC mismatch errors without requiring direct analog intervention.
2Object-generated harmful factors
If conventional correction methods are applied, then distortion is reduced, but noise spectral density increases
Solution Approach 1:
The patent substitutes analog correction methods with digital correction, achieving simultaneous reduction of both distortion and noise spectral density. The digital correction process applies error compensation in the digital domain, avoiding the noise amplification issues inherent in analog correction circuits.
3Productivity
If high-speed conversion is implemented, then productivity increases, but achieving low noise and low distortion simultaneously becomes difficult
Solution Approach 1:
The patent enables high-speed conversion by performing error correction in the digital domain rather than requiring complex analog correction circuits. This digital approach is inherently more suitable for high-speed operation, allowing the ADC to achieve both high conversion speed and superior noise and distortion performance simultaneously.
Data Source
AI summary
Continuous-time (CT) analog-to-digital converters (ADCs) implementing digital correction of digital-to-analog converter (DAC) errors are disclosed. In a CT pipeline stage of a CT ADC, a CT analog input signal is sent to two different paths. A first path (a “feedforward” path) includes a cascade of a sub-ADC and a sub-DAC. A second path (a “forward” path) includes an analog delay circuit to align the delays of the input signal in the feedforward and forward paths. A combiner subtracts the output of the analog delay of the forward path from the output of the sub-DAC in the feedforward path to generate a residue signal. Devices and methods disclosed herein are based on recognition that, if the errors introduced by the sub-DAC are known, they can be corrected in the digital domain during reconstruction, achieving superior NSD and distortion performance compared to conventional approaches.