Current-Controlled MDAC Architecture for Skew-Resilient ADCs
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Solution Overview
Problem
High-speed and high-accuracy analog-to-digital converters (ADCs) face challenges in designing low power solutions due to issues like clock skew, gain and offset errors, and spurious noise in time-interleaved stages, which degrade the output spectrum and overall system performance.
Innovation Solution
A current-mode MDAC-based time-interleaved ADC architecture using a front-end MDAC stage and an array of current-controlled ring oscillator (ICRO) sub-ADCs, combined with efficient calibration techniques, to improve isolation, reduce linearity requirements, and correct non-linearities, while operating at low power and high speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved stages are used to achieve high-speed ADC operation, then sample rate is improved, but clock skew and gain/offset errors introduce spurious noise and degrade output spectrum
Solution Approach 1:
The patent divides the high-speed ADC into multiple time-interleaved sub-ADCs operating at lower individual rates, with each sub-ADC handling a specific time phase. This segmentation allows the overall system to achieve high sample rates while each individual sub-ADC operates at manageable speeds with reduced skew sensitivity.
Solution Approach 2:
The patent implements a feedback mechanism where the output of each time-interleaved sub-ADC is processed and combined with correction techniques. The system uses feedback loops to detect and compensate for clock skew and gain/offset errors, thereby reducing spurious noise and improving output spectrum accuracy.
2Productivity
If time-interleaved stages are used to increase throughput, then productivity is improved, but device complexity increases due to tight clock skew control requirements
Solution Approach 1:
The patent segments the time-interleaved architecture into independent sub-ADC modules, each with its own clock domain. This modular segmentation allows each module to be designed and tested independently, reducing the overall system complexity while maintaining high throughput capability.
Solution Approach 2:
The patent changes the operational parameters of each sub-ADC to operate at relaxed timing conditions compared to a single high-speed ADC. By adjusting the sample rate and timing parameters of individual sub-ADCs, the system achieves high overall throughput without requiring extremely tight clock skew control.
3Use of energy by moving object
If low power operation is implemented in high-speed ADC, then energy consumption is reduced, but manufacturing precision becomes more difficult with 40nm processes and below
Solution Approach 1:
The patent replaces traditional voltage-mode circuitry with current-mode circuitry in the time-interleaved sub-ADCs. This substitution reduces power consumption while current-mode operation is inherently more tolerant of manufacturing variations, thereby addressing both low power and manufacturing precision challenges in advanced 40nm processes.
Solution Approach 2:
The patent changes the operational voltage and current parameters to optimize power efficiency. By operating at lower voltages and optimizing current consumption in each sub-ADC, the system achieves low power operation while the current-mode architecture provides robustness against manufacturing process variations.
Data Source
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AI summary
Current controlled multiplying digital-to-analog converters (MDACs) and related methods are disclosed for time-interleaved analog-to-digital converters (ADCs). For one embodiment, a circuit includes an MDAC having an amplifier that converts a voltage to an output current, a variable load that is dependent upon a digital value and that controls the output current from the amplifier, and an array of comparators that receive the voltage and output the digital value to the variable load. The digital value represents at least a portion of a digital conversion of the voltage. Further, the circuit can include a phased current generator that receives the output current and generates time-interleaved currents where each time-interleaved current is a sampled copy of the output current.