TI-ADC Sub-ADC Assignment for Mismatch Error Estimation
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (TI-ADCs) face challenges with mismatch effects between sub-ADCs, leading to poor spurious-free dynamic range (SFDR) and signal image effects, which are difficult to handle due to the need for error estimation mechanisms that require input signals and may disrupt normal operation.
Innovation Solution
Divide sub-ADCs into two subsets, one for error estimation and one not, and assign input signal samples using different schemes to allow for flexible scheduling and suppression of error estimation impacts, enabling improved error estimation and reduced mismatch effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If error estimation is performed using conventional TI-ADC methods, then mismatch effects can be captured, but the error estimation disrupts normal operation and requires redundant sub-ADCs
Solution Approach 1:
The patent divides the sub-ADCs into two distinct subsets: a first subset dedicated to error estimation and a second subset for normal signal conversion. This segmentation allows error estimation to be performed without disrupting normal operation, as the two functions are executed by separate sub-ADC groups. The control circuit manages this division by assigning different operational modes to different sub-ADCs based on their subset membership.
2Reliability
If redundant sub-ADCs are introduced to handle mismatch effects, then SFDR improves, but device complexity and resource requirements increase
Solution Approach 1:
The patent makes sub-ADCs in the first subset multi-functional by enabling them to operate in two modes: error estimation mode and normal signal conversion mode. During error estimation periods, these sub-ADCs perform mismatch characterization; during normal operation, they convert signals. This eliminates the need for permanently dedicated redundant sub-ADCs, reducing overall device complexity while maintaining SFDR improvement benefits.
Solution Approach 2:
The patent implements periodic error estimation by alternating between error estimation phases and normal operation phases. The control circuit schedules sub-ADCs in the first subset to perform error estimation at specific time intervals rather than continuously. This periodic approach allows the same sub-ADCs to serve both error estimation and signal conversion functions at different times, reducing the number of required sub-ADCs while maintaining reliable error compensation.
3Ease of operation
If sub-ADCs are assigned to samples using fixed schemes, then implementation is simple, but flexibility to suppress error estimation impacts is limited
Solution Approach 1:
The patent introduces dynamic assignment schemes where the control circuit can adaptively select which sub-ADCs process which samples based on real-time conditions. Rather than fixed assignment, the system dynamically adjusts the mapping between sub-ADCs and samples, allowing suppression of error estimation impacts on specific signal components. This dynamic approach maintains implementation simplicity through algorithmic control while providing flexibility to optimize performance for different input signal characteristics.
Data Source
AI summary
A TI-ADC (50) comprising a group of sub-ADCs (A1-AM+N) is disclosed. During operation, M≥2 of the sub-ADCs (A1-AM+N) are simultaneously operated for converting M respective consecutive input signal samples of the TI-ADC (50) from an analog to a digital representation. The total number of sub-ADCs (A1-AM+N) in the group is M+N, N≥1. The TI-ADC (50) comprises error-estimation circuitry (60) for estimating errors of the sub-ADCs (A1-AM+N). Furthermore, the TI-ADC (50) comprises a control circuit (55) configured to, for each input signal sample, assign which sub-ADC (A1-AM+N) is to operate on that input signal sample. The control circuit (55) is configured to, for sub-ADCs (Ak<sup2>1</sup2>) in a first subset of the group of sub-ADCs (A1-AM+N), which are subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a first scheme. Moreover, the control N circuit (55) is configured to, for sub-ADCs (Ak<sup2>2</sup2>) in a second subset of the group of sub-ADCs (A1-AM+N), which are not subject to error estimation by the error-estimation circuitry (60), perform the assignment according to a second scheme, different from the first scheme.