Time-Interleaved ADC Clock Calibration for Timing Skew Polarity
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face challenges due to mismatches between ADCs, leading to timing skew errors that introduce conversion artifacts and reduce accuracy in A/D conversions, particularly when input signals exceed the first Nyquist zone.
Innovation Solution
Implement calibration circuitry to determine the magnitude and polarity of timing skew errors by applying a dither sequence to one clock signal, adjusting the phase of the clock signals based on the polarity of the gain experienced by the dither sequence, and minimizing the difference in similarity measures between adjacent conversions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple ADCs are time-interleaved to increase conversion rate, then productivity is improved, but timing skew errors between ADCs worsen measurement precision
Solution Approach 1:
The patent implements a calibration circuitry that continuously monitors timing skew errors between ADC slices and feeds back correction signals to adjust clock phases. This feedback mechanism dynamically compensates for timing mismatches, allowing the system to maintain high conversion rates while correcting precision errors in real-time.
Solution Approach 2:
The patent changes the phase parameters of clock signals applied to different ADC slices to compensate for timing skew. By adjusting clock phase shifts based on measured errors, the system optimizes the timing alignment between slices while maintaining the high-speed time-interleaved operation.
2Measurement precision
If calibration circuitry is added to correct timing skew, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines the calibration functionality with the existing ADC structure by integrating calibration circuitry into the signal path and sharing clock distribution networks. This merging approach allows timing skew correction without adding completely separate calibration systems, thereby reducing overall complexity.
Solution Approach 2:
The calibration circuitry is designed to automatically detect and correct timing skew errors without requiring external intervention or complex control systems. The system self-calibrates by monitoring its own performance and adjusting clock phases autonomously, simplifying the overall device architecture.
3Measurement precision
If dither sequence is applied to clock signal for polarity detection, then measurement precision is improved, but loss of information increases due to additional processing
Solution Approach 1:
The patent applies a dither sequence to the clock signal, which intentionally adds controlled noise or variation beyond what is strictly necessary for basic operation. This excessive action provides additional information about timing skew polarity that would otherwise be difficult to detect, improving measurement precision at the cost of some processing overhead.
Data Source
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AI summary
An electronic circuit comprises multiple analog-to-digital converters (ADCs), clock circuitry, and calibration circuitry. The clock circuitry is configured to provide clock signals to the multiple ADCs to advance the multiple ADCs through time-interleaved analog-to-digital (A/D) conversions. The calibration circuitry is configured to determine a magnitude of timing skew error between any two of the clock signals; apply a dither sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC; determine a polarity of the timing skew error by determining a polarity of gain experienced by the dither sequence from the time-interleaved A/D conversions.