Interleaved ADC Clock Calibration for Timing Skew Reduction
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Solution Overview
Problem
Interleaved Analog-to-Digital Converters (ADCs) face challenges in achieving high sampling rates due to timing skews and mismatches among channels, leading to spurious tones and reduced dynamic range, particularly when multiple channels are interleaved, requiring a calibration method to introduce programmable delays and correct for sampling pulse-width and component mismatches.
Innovation Solution
A 4-channel interleaved ADC system with product derivative correlators and a matrix processor is used for calibration, employing Successive-Approximation-Register (SAR) delay elements with binary-weighted capacitors to adjust sampling clock phases and compensate for timing skews, while also utilizing overlapping multi-phase clocks and a binary tree of analog input buffers to reduce cross-talk and increase sampling accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If multiple ADC channels are interleaved to achieve higher sampling rates, then the sampling rate is improved, but timing skews and mismatches among channels cause spurious tones and reduced dynamic range
Solution Approach 1:
The patent introduces programmable delay elements that can adjust the timing parameters of each channel by adding variable delays. This allows dynamic adjustment of channel timing to compensate for skews and mismatches, thereby reducing spurious tones and improving dynamic range while maintaining high sampling rates achieved through interleaving
Solution Approach 2:
The patent implements calibration methods that measure timing skews and mismatches among channels, then use this feedback information to adjust programmable delays. This closed-loop approach continuously optimizes channel synchronization, eliminating spurious tones and maintaining high dynamic range performance at elevated sampling rates
2Measurement precision
If programmable delays are introduced to correct timing skews, then timing accuracy is improved, but device complexity increases due to additional calibration circuitry
Solution Approach 1:
The patent divides the delay adjustment function into separate programmable delay elements for each channel, allowing independent timing control. This modular approach simplifies the overall calibration system by breaking down the complex timing synchronization task into manageable per-channel adjustments, reducing overall device complexity while maintaining high timing accuracy
Solution Approach 2:
The patent implements self-calibration methods where the system automatically measures its own timing skews and adjusts delays without external intervention. This self-service approach eliminates the need for complex external calibration equipment and reduces device complexity by making the calibration system autonomous and integrated
3Measurement precision
If sampling pulse width is increased to improve sampling accuracy, then sampling precision is improved, but sampling rate decreases due to longer pulse duration
Solution Approach 1:
The patent uses programmable delay elements that can dynamically adjust timing without requiring longer pulse widths. By making the delay adjustment dynamic and programmable, the system achieves high sampling accuracy through precise timing control rather than extended sampling pulses, thereby maintaining high sampling rates while improving sampling precision
Data Source
AI summary
An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. Each channel receives a sampling clock with a different phase delay. The sampling clocks are overlapping multi-phase clocks rather than non-overlapping. Overlapping the multi-phase clocks allows the sampling pulse width to be enlarged, providing more time for the sampling switch to remain open and allow analog voltages to equalize through the sampling switch. Higher sampling-clock frequencies are possible than when non-overlapping clocks are used. The sampling clock is boosted in voltage by a bootstrap driver to increase the gate voltage on the sampling switch, reducing the ON resistance. Sampling clock and component timing skews are reduced to one LSB among all N channels.