Interleaved ADC Clock Skew Calibration Using Quantized Output Reuse
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing analog-to-digital converter (ADC) technologies face challenges in efficiently calibrating clock skew, leading to increased power consumption and calibration periods due to the need for complex circuits or off-chip calibration methods.
Innovation Solution
An ADC device comprising multiple ADC circuits, a calibration circuit, and a skew adjusting circuit that generates quantized outputs, performs calibration computations, and analyzes time difference information to generate adjusting signals, reducing clock skew through simple computation and frequency-mixed quantized outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If complex circuits (such as additional reference ADC circuits, auxiliary ADC circuits) or off-chip calibration are used to perform calibration, then clock skew calibration capability is achieved, but power consumption and calibration period increase
Solution Approach 1:
The patent combines the clock skew calibration function with the existing ADC circuits by reusing their quantized outputs. Instead of adding separate calibration hardware, the calibration circuit processes the same quantized outputs that the ADC circuits generate during normal operation, merging two functions into a unified system that reduces overall complexity and power consumption.
Solution Approach 2:
The ADC circuits serve dual purposes: they perform their primary analog-to-digital conversion function while simultaneously providing quantized outputs that the calibration circuit uses for clock skew calibration. This multi-functionality eliminates the need for dedicated calibration-only circuits, reducing total power consumption and component count.
2Reliability
If complex circuits (such as additional reference ADC circuits, auxiliary ADC circuits) or off-chip calibration are used to perform calibration, then clock skew calibration capability is achieved, but calibration period increases
Solution Approach 1:
The calibration function is merged with the existing ADC operation timeline. The calibration circuit processes quantized outputs that are already being generated during normal ADC operation, allowing calibration to occur within the existing operational framework rather than requiring separate calibration time periods.
Solution Approach 2:
The calibration circuit continuously processes quantized outputs in the background during normal ADC operation, performing calibration computations preliminarily rather than waiting for dedicated calibration intervals. This allows the system to maintain calibration readiness without stopping or slowing down the primary conversion function.
3Measurement precision
If additional reference ADC circuits or auxiliary ADC circuits are added for calibration, then clock skew calibration accuracy is improved, but device complexity increases
Solution Approach 1:
The patent merges the calibration function with existing ADC circuits by reusing their quantized outputs. Instead of adding separate calibration hardware, the calibration circuit processes the same quantized outputs that the ADC circuits generate during normal operation, merging two functions into a unified system that reduces overall complexity.
Solution Approach 2:
The ADC circuits provide their own quantized outputs that serve as input for the calibration process. The system uses its own operational data for calibration purposes, eliminating the need for external or auxiliary calibration circuits and achieving self-service calibration that reduces device complexity.
Data Source
AI summary
An analog to digital converter (ADC) device includes ADC circuits, a calibration circuit, and a skew adjusting circuit. The ADC circuits convert an input signal according to interleaved clock signals, in order to generate first quantized outputs. The calibration circuit performs at least one calibration computation according to the first quantized outputs to generate second quantized outputs. The skew adjusting circuit determines maximum value signals, to which the second quantized outputs correspond in a predetermined interval, and averages the maximum value signals to generate a reference signal, and compares the reference signal with each of the maximum value signals to generate detecting signals, and determines whether the detecting signals are adjusted or not according to a signal frequency to generate adjusting signals, in order to reduce a clock skew in the ADC circuits.