Continuous-Time Pipeline ADC Filter Calibration for Path Matching

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Solution Overview

Problem

Continuous-time pipeline ADCs face performance degradation due to mismatches between digital and analog paths, which affect the accuracy of digital signal reconstruction.

Innovation Solution

A continuous-time analog-to-digital converter circuit is proposed, featuring a digital filter that replicates the transfer function of the continuous-time filter in the digital domain, allowing for improved matching between analog and digital paths. This is achieved through a calibration method that adjusts filter coefficients using a calibration device and algorithm, such as the normalized LMS algorithm.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If digital filter coefficients are not calibrated to match the analog path, then device complexity is reduced, but measurement precision degrades due to mismatch between digital and analog paths

Engineering Contradiction:
Improvematching accuracy between digital and analog pathsVSAvoidcalibration system complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent creates a digital copy (replica) of the continuous-time filter's transfer function in the digital domain. The digital filter is designed to replicate the analog filter's frequency response characteristics, allowing the digital path to match the analog path without requiring complex physical calibration hardware. This copying approach resolves the contradiction by achieving high measurement precision through digital replication rather than complex calibration systems.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The patent replaces potential hardware-based calibration mechanisms with a software/digital signal processing approach. By using digital filtering and transfer function replication, the system achieves path matching without requiring additional analog calibration components or complex mechanical adjustment mechanisms, thus reducing device complexity while maintaining measurement precision.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

2Reliability

If the gain of the analog filter block is increased to improve performance, then ADC performance is improved, but mismatch between digital and analog paths worsens

Engineering Contradiction:
ImproveADC performanceVSAvoidpath matching accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent implements a feedback mechanism where the digital filter continuously adjusts its output to compensate for the analog filter's gain. The digital filter's transfer function is designed to include compensatory elements that counteract the analog filter's frequency response, creating a closed-loop system where the digital path adaptively matches the analog path even at high gain levels, thus resolving the contradiction between improved ADC performance and maintained path matching accuracy.

Inventive Principle:
Principle #23Feedback

Data Source

PatentEP4568112A1Continuous-time pipeline ADC and method for calibrating a digital filter of a continuous-time pipeline ADC
Publication Date: 2025.06.11 NXP BV
  • EP4568112A1 patent drawingFigure 1
  • EP4568112A1 patent drawingFigure 2
  • EP4568112A1 patent drawingFigure 3

AI summary

A continuous-time analog-to-digital converter circuit (100), comprising: - an input (1) configured to receive an analog input signal (vin); - a delay element (10) with a specified time delay (td), the delay element (10) functionally connected between the input (1) and a first summation node (20); - a ADC-DAC path with a sub ADC (11) and a sub DAC (12) connected between the input (1) and the first summation node (20), the ADC-DAC path configured to digitize the analog input signal (vin) and to reconvert the digitized signal to analog domain and to subtract it at the first summation node (20); - wherein an output of the first summation node (20) is filtered by means of a continuous-time filter (30), wherein an output of the continuous-time filter (30) is clocked by a specified sampling rate (fs); - wherein a backend ADC (41) is configured to digitize the clocked output of the analog filter (30) and to connect the clocked output to a second summation node (42); - wherein an output (v) is obtained by a summation of the output of the backend ADC (41) and an output of a digital filter (40) being connected to the sub ADC (11), characterized in that the digital filter (40) is configured to represent a replica of a transfer function of the sampled output of the continuous-time filter (30) in the digital domain.