Pipeline A/D Converter Staging for Fast Accurate Sampling
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Solution Overview
Problem
Existing pipeline A/D converter circuits do not disclose configurations that operate at faster clocks and appropriate bit numbers for downstream stages, leading to inefficiencies in sampling and conversion accuracy.
Innovation Solution
The A/D converter circuit includes a first pipeline stage outputting x bits, a second pipeline stage outputting y bits smaller than x, and an A/D converter that samples the second stage's output in a shorter sampling period, performing A/D conversion to output a third digital value, with a cyclic or successive approximation A/D converter enhancing conversion speed and accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the sampling period is reduced to increase conversion speed, then productivity is improved, but measurement precision deteriorates
Solution Approach 1:
The patent divides the A/D conversion process into multiple pipeline stages, where each stage performs partial conversion. The first pipeline stage performs initial conversion, and a second A/D converter performs additional conversion on the remaining signal. This segmentation allows the system to achieve high-speed conversion (short sampling period) while maintaining precision through multiple conversion passes rather than requiring a single long conversion cycle.
2Measurement precision
If the number of bits in downstream stage is increased to improve precision, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent applies different bit resolutions to different stages of the conversion process. The first pipeline stage operates with a specific bit depth, and the second A/D converter operates with a different bit depth optimized for the remaining signal characteristics. This local optimization allows each stage to use the appropriate precision level for its function, avoiding the need for uniformly high precision throughout the entire system, thus reducing overall complexity while maintaining accuracy.
Data Source
AI summary
An A/D converter circuit includes a first pipeline stage outputting a first digital value of x bits by A/D conversion based on an input signal, a second pipeline stage outputting a second digital value of y bits smaller than the x bits by A/D conversion based on a first analog output signal of the first pipeline stage, and an A/D converter sampling a second analog output signal of the second pipeline stage in a sampling period shorter than a sampling period of the first pipeline stage and a sampling period of the second pipeline stage, performing A/D conversion based on a sampling result, and outputting a third digital value.