ADC Latch Clock Sharing to Cut Wiring and Footprint
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Solution Overview
Problem
Existing analog-to-digital (A/D) converters face challenges in reducing the footprint and power consumption of primary/secondary latch circuits in IC-chip A/D converters, leading to unstable operations and performance limitations due to increased parasitic impedance and component layout space requirements.
Innovation Solution
The implementation of a pulse delay circuit with a series connection of delay units, where each latch module includes primary and secondary latches that share a common clock, reducing the number of clock wirings and minimizing the footprint without increasing the number of pulse delay circuits or delay units, thereby stabilizing operations and improving performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the number of clock wirings is increased to provide separate clocks to each secondary latch, then each latch can operate independently, but the footprint and parasitic impedance increase
Solution Approach 1:
Multiple secondary latches share a common clock signal instead of each having a separate clock wiring. This merging of clock resources reduces the number of clock wirings and minimizes the latch circuit footprint while maintaining stable operation through the shared clock distribution.
2Device complexity
If separate clock wirings are provided to each secondary latch, then clock distribution is simplified, but parasitic impedance and power consumption increase
Solution Approach 1:
The patent merges multiple clock wirings into a single common clock signal that serves all secondary latches. This reduces the total wiring length and number of connections, thereby decreasing parasitic impedance and power consumption associated with clock distribution.
3Measurement precision
If more clock wirings are used for each secondary latch, then timing control is more precise, but manufacturing cost increases
Solution Approach 1:
By combining multiple separate clock wirings into a single common clock signal, the patent reduces the complexity of the wiring layout and decreases the number of manufacturing steps required for clock distribution, thereby lowering manufacturing costs while maintaining adequate timing control precision.
Data Source
AI summary
In an analog-to-digital converter, primary latches respectively latch an output of a corresponding one of delay units at respective sample times of different first clocks. The primary latches include at least first and second primary latches, and secondary latches include at least first and second secondary latches respectively corresponding to the at least first and second primary latches. Each of the at least first and second secondary latches is configured to latch, at a sample time of a common second clock, an output of a corresponding one of the at least first and second primary latches. The common second clock is based on at least one of the first clocks.