Clockless Charge-to-Digital Conversion with Dual Sampling Capacitors
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Solution Overview
Problem
Existing clock-based conversion methods for electric charge to digital words in monitoring and control systems require a break for redistribution and relaxation phases, leading to inefficiencies and increased energy consumption.
Innovation Solution
A clockless method and apparatus that accumulate electric charge in a sampling capacitor and an additional capacitor with the highest capacitance, allowing continuous conversion of two charge portions without breaks, using a control module to manage redistribution and assignment of digital values, reducing energy consumption and conversion time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If clock-based conversion method is used, then conversion process is structured and controllable, but conversion time increases due to required break periods for redistribution and relaxation phases
Solution Approach 1:
The patent implements continuous conversion by eliminating idle break periods between conversions. The apparatus maintains continuous operation by immediately initiating the next conversion cycle after the current one completes, with the sampling capacitor ready to accumulate charge without waiting for redistribution or relaxation phases to finish. This continuous operation directly addresses the time loss issue while maintaining structured control through the control module.
2Reliability
If traditional redistribution phase is implemented, then charge is properly distributed across capacitors, but energy consumption increases
Solution Approach 1:
The patent performs preliminary charge accumulation in the sampling capacitor during the active state of the gate signal, before the conversion process officially begins. By having the charge already accumulated and ready in the sampling capacitor, the system eliminates or reduces the need for extensive redistribution phases, thereby reducing energy consumption while ensuring accurate charge representation is already prepared for conversion.
3Measurement precision
If sampling capacitor accumulates charge continuously, then conversion accuracy is maintained, but converter area increases
Solution Approach 1:
The sampling capacitor serves multiple functions: it accumulates charge during the active state, holds the charge ready for conversion, and acts as the primary storage element eliminating the need for separate large-capacity redistribution capacitors. This multi-functionality maintains measurement precision through continuous charge accumulation while reducing the overall converter area by consolidating storage requirements into a single versatile component.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient conversion of two charge portions with minimal delay, reduces energy consumption, and decreases the area required for the converter, while maintaining accuracy and reducing the time for charge redistribution by at least 25%.
Implementation Method 1
accumulation of electric charge delivered to the charge input InQ in the sampling capacitor Cn
Implementation Method 2
the process of redistribution of the accumulated electric charge is realized in the array of redistribution A
Data Source
Figure 1
Figure 2
Figure 3~4
AI summary
Method consists in accumulation of electric charge delivered to the charge input (InQ) in the sampling capacitor (Cn) and in realization of the process of charge redistribution in the array of redistribution (A) by changing states of signals from relevant control outputs and in assignment of relevant values to bits in the digital word by means of the control module (CM). Method is characterized in that after detection of the beginning of the next gate signal (Gx+1), the charge is accumulated in the additional sampling capacitor (CnA), and then the process of charge redistribution is realized and relevant values are assigned to bits of the digital word. When the beginning of the subsequent gate signal (Gx+2) is detected, the next cycle begins and electric charge is accumulated in the sampling capacitor (Cn) again. Apparatus comprises the array of redistribution (A), the section of the sampling capacitor (An), the control module (CM), two comparators (K1 and K2) and the current source (J) connected in a known way. Apparatus is characterized in that the additional sampling capacitor (CnA) and the top plate change-over switches (STn, STnA, SBn, SBnA) and the charge input (InQ) and the input on-off switch (SQ) are connected in the section of the sampling capacitor (An). Furthermore, the additional capacitor (Cn-1A) having the highest capacitance value in the array of redistribution and the bottom plate change-over switches (STn-1, STn-1A, SBn-1, SBn-1A) are connected to the capacitor (Cn-1) having the highest capacitance value in the array of redistribution in a similar way as to the sampling capacitor (Cn).