Parallel SAR ADC Architecture for Shorter Multi-Bit Conversion Time
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Solution Overview
Problem
Conventional successive approximation register (SAR) ADC circuits experience increased conversion time as the number of bits in the digital output signal increases, leading to inefficiencies in processor-based systems that rely on analog-to-digital conversion.
Innovation Solution
The implementation of multiple-bit parallel SAR ADC circuits, which utilize multiple SAR controller circuits and digital-to-analog converter (DAC) circuits to generate digital bits in parallel, reducing conversion time by generating multiple digital bits simultaneously using a reference voltage and compare circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional SAR ADC circuits are designed to generate digital output signals with a greater number of bits, then the precision of the digital output signal is improved, but the conversion time increases
Solution Approach 1:
The patent divides the conversion process into multiple independent segments by implementing multiple SAR controller circuits (first SAR controller, second SAR controller, etc.) that each handle specific bit positions in parallel. This segmentation allows the ADC to determine multiple digital bits simultaneously rather than sequentially, thereby improving conversion speed while maintaining high precision for multi-bit digital output signals
Solution Approach 2:
The patent transitions from a single-dimensional sequential conversion process to a multi-dimensional parallel processing architecture. By introducing multiple SAR controller circuits operating simultaneously on different bit positions, the system adds a spatial dimension to the conversion process, enabling multiple comparisons and bit determinations to occur concurrently, thus reducing conversion time without sacrificing precision
2Measurement precision
If conventional SAR ADC circuits are designed to generate digital output signals with a greater number of bits, then the resolution of the digital output signal is improved, but the number of circuit elements increases
Solution Approach 1:
The patent implements universal SAR controller circuits that can handle multiple bit positions through parallel operation. Each SAR controller circuit is designed with multi-functional capability to perform comparison and bit determination operations for specific bit ranges, allowing the system to achieve high resolution digital output signals while reusing similar circuit blocks rather than requiring entirely separate circuits for each bit, thus managing device complexity more efficiently
3Measurement precision
If conventional SAR ADC circuits are designed to generate digital output signals with a greater number of bits, then the accuracy of the digital output signal is improved, but the conversion speed decreases
Solution Approach 1:
The patent segments the digital output signal into multiple bit groups that can be processed in parallel by different SAR controller circuits. Each controller is responsible for determining specific bits (e.g., most significant bits, middle bits, least significant bits) simultaneously, which maintains high accuracy for the complete digital output signal while dramatically improving conversion speed through parallel bit determination
Solution Approach 2:
The patent transforms the single-threaded sequential bit determination process into a multi-threaded parallel architecture by introducing multiple SAR controller circuits operating concurrently on different bit positions. This dimensional expansion from sequential to parallel processing enables the system to maintain high accuracy for multi-bit digital signals while achieving faster conversion speeds through simultaneous operation
Data Source
AI summary
Multiple-bit parallel successive approximation register (SAR) analog-to-digital converter (ADC) circuits are disclosed. In one aspect, a multiple-bit parallel SAR ADC circuit includes a number of SAR controller circuits, each of which includes SAR register circuits. Each SAR register circuit receives and stores a corresponding digital bit that is based on a comparison of an analog input signal and a corresponding digital-to-analog converter (DAC) analog signal. Each SAR register circuit also provides a corresponding digital signal based on the digital bit. A DAC circuit receives a reference voltage, and uses the reference voltage and a subset of digital signals generated by SAR controller circuits to generate multiple DAC analog signals. A compare circuit generates the digital bit corresponding to each SAR controller circuit, wherein a number of the digital bits are generated in parallel. Each digital bit collectively forms a digital representation of the analog input signal.