MUTEX Signal Ordering Circuit for Metastability-Tolerant TDCs
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Solution Overview
Problem
Metastability in asynchronous RS flip-flops within TDC-type analog-to-digital converters can lead to incorrect signal ordering and prolonged processing times, affecting the accuracy of time interval measurements in applications like laser rangefinders and VLSI circuit testing.
Innovation Solution
The system incorporates a main MUTEX circuit with additional delay circuits and OR/AND logic gates to manage metastability by assigning default values to bits at risk of falsification, ensuring correct operation and reducing processing time and energy consumption, even during metastability events.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a forbidden state filter is added to prevent metastability effects in MUTEX circuits, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by introducing delay circuits before the MUTEX circuit to ensure that signals are properly synchronized and ready before entering the MUTEX. The delay circuits are configured to provide a delay time that is at least as long as the maximum propagation time of the MUTEX circuit, ensuring that metastability conditions are avoided before they can occur. This preventive approach eliminates the need for complex forbidden state filters while maintaining reliability.
Solution Approach 2:
The patent extracts the delay function from within the MUTEX circuit structure and places it in separate delay circuits connected to the inputs. By taking out the timing control function and implementing it independently through delay circuits with controllable delay times, the design simplifies the overall MUTEX structure while maintaining reliable operation without requiring forbidden state filters.
2Reliability
If delay circuits are used to synchronize signals before MUTEX, then metastability is reduced, but device complexity increases
Solution Approach 1:
The delay circuits serve multiple functions: they synchronize the input signals to the MUTEX circuit, provide timing control, and can be adjusted to match different propagation delays in the system. By making the delay circuits controllable and multi-functional, the design achieves reliable metastability prevention without adding excessive complexity, as the same components serve multiple purposes in the signal path.
3Speed
If the MUTEX circuit propagation delay is reduced, then processing speed is improved, but signal synchronization becomes more difficult
Solution Approach 1:
The patent implements dynamics by making the delay circuit delay time controllable and adjustable. The delay circuits can dynamically adapt their delay amount based on the actual propagation delays in the system and the timing requirements of the MUTEX circuit. This dynamic adjustment capability allows the system to maintain reliable synchronization even when the MUTEX propagation delay is reduced, as the delay circuits can be tuned to compensate for the faster MUTEX response.
Data Source
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AI summary
A system for recognizing an order of signals comprise a main MUTEX circuit (MMx), a first delay circuit (TM1x), a second delay circuit (TM1x) and a path configuration circuit (Ex). The system is characterized in that inputs of the main MUTEX circuit (MMx) are connected to inputs of a first gate (B1), whose output is connected to an additional delay circuit (TDx), and its output is connected to a reset input (R) of an additional MUTEX circuit (MAx). Outputs of the main MUTEX circuit (MMx) are connected to inputs of a second gate (B2), whose output is connected to a set input (S) of the additional MUTEX circuit (MAx). A second output (Q2) of the additional MUTEX circuit (MAx) is connected to a priority input (Prtx) of an output module (OM).