Segmented Delta-Sigma ADC for Faster, Area-Efficient Conversion
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Solution Overview
Problem
Existing ADC architectures, such as SAR and flash ADCs, are inefficient in terms of area and power, while conventional delta-sigma ADCs have longer conversion times, posing challenges for memory systems as they scale down in size.
Innovation Solution
An n-split delta sigma ADC architecture that splits the input analog signal range into n+1 sub-ranges, assigning an N-bit digital code to each sub-range and performing a delta-sigma operation using reference voltages, resulting in a more area-efficient and faster conversion process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional delta-sigma ADC architecture is used, then high resolution is achieved, but conversion time becomes too long
Solution Approach 1:
The patent divides the ADC conversion process into multiple parallel sub-ranges (e.g., 8 sub-ranges for 3-bit segmentation). Each sub-range is processed simultaneously by dedicated comparator circuits, transforming a sequential high-resolution conversion into parallel operations. This segmentation reduces the number of conversion steps required while maintaining overall resolution through digital reconstruction of the segmented results.
2Speed
If flash ADC architecture is used, then conversion speed is improved, but area efficiency deteriorates
Solution Approach 1:
The patent segments the full-scale voltage range into multiple sub-ranges, each handled by a smaller number of comparators. Instead of requiring 2^N-1 comparators for an N-bit flash ADC, the segmented architecture uses (2^k-1) comparators per sub-range where k < N, with multiple sub-ranges processed in parallel. This dramatically reduces the total comparator count and circuit area while maintaining conversion speed through parallel operation.
Solution Approach 2:
The patent transitions from a single-dimensional sequential comparison approach to a multi-dimensional parallel processing structure. By organizing comparators into multiple sub-range blocks that operate simultaneously and combining their outputs through digital logic, the system achieves flash-like speed with segmented architecture, effectively adding the dimension of parallel processing to reduce area requirements.
3Area of stationary object
If SAR ADC architecture is used, then area efficiency is improved, but conversion time increases
Solution Approach 1:
The patent implements parallel segmented conversion where multiple sub-range comparisons occur simultaneously rather than sequentially as in SAR ADC. Each segment performs its conversion in parallel, and the results are combined digitally, eliminating the iterative sequential search process of traditional SAR ADC while using comparable area-efficient circuitry.
Data Source
AI summary
Systems and methods for converting an input analog signal to a digital representation thereof. A method includes determining an input analog signal voltage range of the input analog signal, and splitting the input analog signal voltage range into n+1 sub-ranges, n being a number of splits in the input analog signal voltage range. The method also includes assigning a respective N-bit coarse digital code i to each sub-range. The method also includes identifying the input analog signal with a corresponding sub-range, the corresponding sub-range having respective digital code i. A delta-sigma operation is performed on the input analog signal using upper and lower reference voltages of the corresponding sub-range that the input analog signal is identified with, to produce the digital representation.