Time-Interleaved ADC Calibration Using Reference Zero-Crossing

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Solution Overview

Problem

Time-interleaved analog-to-digital converter (ADC) circuits face challenges in calibration due to mismatches between sub-ADCs, leading to errors such as DC-offsets, gain mismatches, and sampling time errors, which existing calibration techniques struggle to address efficiently and reliably, especially in high-bandwidth wireless transceivers for 5G standards.

Innovation Solution

A high-speed, low-resolution reference ADC is used for calibration, operating at the same sample rate as the sub-ADCs, with only three comparators to detect polarity, eliminate offset and gain mismatches, and correct timing errors, allowing for background calibration without sub-sampling disturbances.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a high-resolution reference ADC is used for calibration, then measurement precision is improved, but power consumption and device complexity increase

Engineering Contradiction:
Improvecalibration accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent uses a low-resolution copy (1-bit or few-bit reference ADC) instead of a full high-resolution reference ADC. This copy provides sufficient calibration information for offset and gain correction without requiring the full resolution, thereby reducing power consumption and complexity while maintaining adequate calibration precision.

Inventive Principle:
Principle #26Copying

Solution Approach 2:

The reference ADC is designed with minimal resolution (1-bit or few-bit) specifically for calibration purposes. This simplified, lower-cost component performs the calibration function adequately without needing the full performance of a high-resolution ADC, reducing both power consumption and hardware complexity.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

2Use of energy by moving object

If a low-speed reference ADC is used for calibration, then power consumption is reduced, but calibration reliability deteriorates due to sub-sampling disturbances

Engineering Contradiction:
Improvepower consumptionVSAvoidcalibration reliability
Core Design Contradiction:
Use of energy by moving objectVSReliability

Solution Approach 1:

The patent preemptively addresses the sub-sampling distortion problem by designing the calibration algorithm to compensate for these known distortions. The system predicts and counteracts the expected errors from low-speed sampling, allowing reliable calibration even with a low-speed reference ADC.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The patent changes the operating parameters of the reference ADC, specifically using a low sampling rate that is a fraction of the main ADC rate. By adjusting the sampling rate parameter and compensating through algorithmic correction, the system achieves power efficiency without sacrificing calibration reliability.

Inventive Principle:
Principle #35Parameter changes

3Extent of automation

If statistics-based calibration is used, then automation is improved, but measurement precision deteriorates when input signal statistics are not well-behaved

Engineering Contradiction:
Improvecalibration automationVSAvoidcalibration accuracy
Core Design Contradiction:
Extent of automationVSMeasurement precision

Solution Approach 1:

The calibration system uses the actual input signal itself for calibration rather than requiring separate test signals or assumptions about signal statistics. The reference ADC samples the same input signal that the main ADC processes, allowing the system to self-calibrate using real operating conditions, improving both automation and precision.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11323128B2Calibration technique for time-interleaved analog-to-digital converters
Publication Date: 2022.05.03 TELEFONAKTIEBOLAGET LM ERICSSON (PUBL)
  • US11323128B2 patent drawing
  • US11323128B2 patent drawing
  • US11323128B2 patent drawing

AI summary

A reference analog-to-digital converter (ADC) samples an input signal in parallel with sub-converters of a time-interleaved ADC. For each sub converter and for each of a plurality of output samples from the sub-converter, a calibration circuit determines whether the output sample from the sub-converter indicates an input signal polarity opposite that indicated by the reference ADC. For each such instance, a DC-offset sample is calculated as a difference between the output sample from the sub-converter and a target zero-crossing value for the sub-converter output. For each sub-converter, a series of DC-offset samples is filtered, to produce an average zero-crossing error for each sub-converter. This filtering may comprise a simple average, for example, or a moving average, a decaying filter, etc. Finally, a zero-crossing correction is applied for each of one or more of the sub-converters, based on the respective average zero-crossing error.