Dual-Loop Chopping Switch Calibration in Time-Interleaved ADCs
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Solution Overview
Problem
Time-interleaved analog-to-digital converters (ADCs) face challenges in calibrating time-skew errors of chopping switches, which introduces significant noise due to the doubling of sampling times and non-uniform sampling intervals, complicating the calibration process.
Innovation Solution
A time-skew calibration circuit and method that synchronizes the chopping sequence with a calibration observation window, inverts polarity halfway through, and executes a dual-loop calibration to effectively handle the increased complexity and noise introduced by chopping switches, ensuring reliable background calibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If chopping switches are added to time-interleaved ADC to reduce offset and flicker noise, then offset error and flicker noise are spread across frequency, but sampling time mismatch of the new switches degrades the converter noise floor
Solution Approach 1:
The patent implements a feedback-based calibration system that measures the sampling time mismatch of chopping switches and applies correction signals to compensate for the mismatch. The calibration circuit continuously monitors the timing errors and adjusts the chopping switch timing to minimize noise floor degradation while maintaining the benefits of offset and flicker noise reduction.
Solution Approach 2:
The patent dynamically adjusts the timing parameters of the chopping switches through calibration. By changing the sampling time parameters of the chopping switches based on measured mismatch conditions, the system optimizes the trade-off between noise reduction benefits and noise floor degradation, ensuring optimal performance across varying operating conditions.
2Measurement precision
If multiple accumulators and adders are used for dual-loop calibration, then calibration accuracy is improved, but circuit complexity increases
Solution Approach 1:
The patent divides the calibration process into two independent loops, each handling specific aspects of time-skew calibration. The first loop calibrates the chopping switch timing while the second loop calibrates the time-interleaved channel timing. This segmentation allows each loop to be optimized independently and simplifies the overall calibration control logic despite using multiple accumulators and adders.
Solution Approach 2:
The calibration circuit uses shared accumulators and adders that serve multiple functions across both calibration loops. The same hardware resources are reused for different calibration tasks, reducing the overall circuit complexity while maintaining the precision benefits of dual-loop calibration. The circuit elements are designed to handle multiple calibration functions efficiently.
Data Source
AI summary
An example time-skew calibration circuit includes a plurality of first circuits, each including a first accumulator and a second accumulator. The time-skew calibration circuit further includes a plurality of second circuits, each including a first adder coupled to outputs of the first accumulator and the second accumulator, and a first subtractor coupled to the outputs of the first accumulator and the second accumulator. The time-skew calibration circuit further includes a decision circuit configured to combine an output of the first adder and an output of the first subtractor.