Differential Voltage-to-Delay Converter With Calibrated Linearity
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Solution Overview
Problem
Existing delay domain analog-to-digital converters (ADCs) face significant non-linearity issues due to transistor saturation margins at low power supply voltages, leading to compressive gain characteristics that affect the accuracy and performance of high data rate communications devices, particularly in mobile and battery-powered devices like 5G user equipment.
Innovation Solution
A voltage-to-delay converter design incorporating a dynamic differential amplifier with a constant current discharge stage and calibration logic to adjust common mode voltage, which compensates for non-linearity by combining compressive and expansive gain characteristics, ensuring improved linearity over variations in input voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dynamic differential amplifier is used in voltage-to-delay converter, then conversion speed and data rate are improved, but non-linearity and gain compression occur due to transistor saturation margins at low power supply voltages
Solution Approach 1:
The voltage-to-delay converter is divided into two independent legs (first leg with first integrating capacitor and second leg with second integrating capacitor), each processing one differential input voltage. This segmentation allows independent optimization of each leg's discharge characteristics, enabling better control over saturation margins and linearity while maintaining high conversion speed.
Solution Approach 2:
The patent applies parameter changes by dynamically adjusting the discharge current based on the input voltage level. When the input voltage exceeds a threshold, the discharge current is modified to prevent transistor saturation, thereby maintaining linearity. This is achieved through calibration logic that adjusts operating parameters to compensate for gain compression effects.
2Use of energy by moving object
If low power supply voltage is used to reduce power consumption, then power efficiency is improved, but transistor saturation margins are reduced causing compressive gain characteristics
Solution Approach 1:
The patent implements dynamic operation by using a dynamic differential amplifier where transistors are switched between different operating states during the conversion cycle. The amplifier operates in a controlled saturation region during the integration phase, then resets to a linear region during the discharge phase. This dynamic switching allows efficient operation at low supply voltages while maintaining linearity through proper timing and control.
Solution Approach 2:
The calibration logic performs preliminary adjustment of the discharge parameters before the actual voltage-to-delay conversion. By pre-calibrating the discharge current and timing based on expected input conditions, the system compensates for potential saturation effects before they occur, ensuring linear operation even at low power supply voltages.
3Productivity
If integrating capacitors are discharged at high rate to improve conversion speed, then data rate is improved, but transistor saturation occurs reducing accuracy
Solution Approach 1:
The patent incorporates calibration logic that monitors the discharge process and provides feedback control. The calibration logic adjusts the discharge current and timing based on the state of the integrating capacitors and the input voltage level. This feedback mechanism ensures that the discharge rate remains optimal for high data rate operation while preventing transistor saturation, thereby maintaining conversion accuracy.
Data Source
AI summary
A voltage-to-delay converter includes a first reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving a reset signal, and a second terminal coupled to a top plate of a first integrating capacitor, and a second reset transistor having a first terminal coupled to a power supply terminal, a gate terminal receiving the reset signal, and a second terminal coupled to a top plate of a second integrating capacitor. First and second input transistors receive first and second input voltages, and are coupled between the top plate of the first and second integrating capacitors, respectively, and a first current source. A discharge current source is coupled to bottom plates of the first and second integrating capacitors. A pulse generator has first and second inputs coupled to the top plate of the first and second integrating capacitors, respectively.