Successive Approximation ADC Architecture for High Resolution in Less Area
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Solution Overview
Problem
Successive approximation analog-digital converters face limitations in achieving high precision due to inaccuracies that degrade digital resolution beyond 10 bits, leading to increased complexity and surface area requirements in embedded systems.
Innovation Solution
A two-bit successive approximation converter architecture that shares a single calculator and comparator, using a sample-and-hold module to sample the voltage and compare it to multiple reference voltages, reducing conversion errors and complexity while maintaining precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional successive approximation converter is used to achieve high digital resolution, then the precision is improved, but the converter surface area and complexity increase significantly
Solution Approach 1:
The patent merges multiple calculator functions into a single shared calculator that is reused across different conversion stages. The same calculator hardware is used to compute intermediate voltages for multiple bits, reducing the total number of calculators from n (for n-bit resolution) to a single shared unit, thereby significantly reducing surface area while maintaining precision
Solution Approach 2:
The shared calculator is designed to perform multiple functions: it calculates intermediate voltages for different bits, works with different comparison voltages, and serves multiple conversion stages. This multi-functional design allows one calculator to replace what would traditionally require multiple dedicated calculators, reducing overall converter complexity and area
2Measurement precision
If the number of conversion bits is increased to achieve higher precision, then the digital resolution is improved, but the device complexity increases
Solution Approach 1:
The patent combines multiple conversion operations into a unified architecture where a single shared calculator and comparator handle conversions for multiple bits. Instead of having separate calculation paths for each bit, the system merges these functions into shared resources that are time-multiplexed across different conversion stages, reducing device complexity
Solution Approach 2:
The system dynamically reconfigures the shared calculator and comparator to serve different conversion stages at different times. The same hardware components are dynamically assigned to different bits and comparison voltages based on the current conversion phase, allowing high precision without proportionally increasing static device complexity
3Measurement precision
If multiple calculators are used to maintain precision across multiple conversion stages, then the measurement precision is improved, but the surface area required increases
Solution Approach 1:
The patent merges the calculation functions for all conversion stages into a single shared calculator. This calculator computes intermediate voltages for multiple bits sequentially, using the same hardware resources throughout the conversion process. This approach maintains conversion precision while reducing the surface area required for calculator components
Data Source
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AI summary
The invention relates to an analog-to-digital converter which includes a first stage in which a voltage to be converted (Vin) is applied to the input of a first comparator (2). The first comparator (2) outputs, via a first digital output, a first digital result (Bi) which represents the comparison between the voltage to be converted (Vin) and the comparison voltage (Vref). The first digital output is connected to a calculator (3) of a first intermediate voltage (V1). A second comparator (5) compares the first intermediate voltage (V1) with the comparison voltage (Vref) and outputs a second digital result (Bi+1) via a second digital output terminal. The second digital output terminal is connected to a second calculator of a residual voltage that is a function of the voltage to be converted (Vin), of first (Va) and second (Vb) voltages and of the first and second digital results (Bi, Bi+1). The first calculator is formed by the second calculator.