Pipeline Sub-ADC MSB Detection During Input Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Pipelined analog-to-digital converters (ADCs) face challenges in determining the most-significant bit (MSB) during the sampling process, which affects processing speed and power consumption, particularly in high-resolution applications where initiating digital bit conversion after sampling is complete.
Innovation Solution
Configuring at least one sub-ADC in a pipelined ADC to determine the MSB while the input signal is being sampled, reducing the need for additional comparators and allowing simultaneous bit conversion operations across stages, thereby enhancing processing speed and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If digital bit conversion is initiated after sampling is complete, then conversion accuracy is maintained, but processing speed decreases and power consumption increases
Solution Approach 1:
The patent applies preliminary action by determining the most-significant bit (MSB) during the sampling phase, before the complete sampling process finishes. This allows the conversion process to start earlier and proceed in parallel with the remaining sampling operations, thereby reducing total conversion time and improving processing speed without compromising accuracy
2Productivity
If additional comparators are added to determine MSB during sampling, then processing speed improves, but device complexity increases
Solution Approach 1:
The patent implements multi-functionality by configuring existing comparators to serve dual purposes: they continue their traditional role in digital bit conversion while simultaneously determining the most-significant bit (MSB) during the sampling phase. This eliminates the need for additional dedicated comparators, maintaining high throughput without increasing device complexity
3Measurement precision
If MSB determination is performed after sampling completes, then measurement precision is ensured, but power consumption increases
Solution Approach 1:
The patent applies continuity of useful action by performing MSB determination continuously during the sampling process rather than waiting for sampling to complete. This overlapping execution allows the conversion process to proceed without idle waiting time, improving energy efficiency while maintaining measurement precision through the coordinated operation of comparators throughout the sampling period
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
An analog-to-digital converter (ADC) configured to convert an analog signal to digital bits. The ADC includes a plurality of sub-ADCs that are cascaded in a pipeline. Each sub-ADC may be configured to sample an input signal that is fed to each sub-ADC and convert the sampled input signal to a pre-configured number of digital bits. Each sub-ADC except a last sub-ADC in the pipeline is configured to generate a residue signal and feed the residue signal as the input signal to a succeeding sub-ADC in the pipeline. At least one sub-ADC is configured to determine a most-significant bit (MSB) of the pre-configured number of digital bits while the input signal is sampled. The ADC may include a plurality of residue amplifiers for amplifying a residue signal. The sub-ADCs may be successive approximation register (SAR) ADCs or flash ADCs.