ADC Sampling Clock Delay for IQ Phase Imbalance Calibration

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Solution Overview

Problem

Wireless communication systems face performance degradation due to IQ phase imbalance between in-phase (I) and quadrature (Q) signal channels, which conventional calibration methods fail to adequately address.

Innovation Solution

A system and method for IQ phase imbalance calibration using sampling clock delay adjustment, synchronizing the sampling of I and Q signals, and applying a sampling delay to compensate for phase imbalance through a sampling clock delay circuitry.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If conventional calibration techniques using asymmetric filters, variable phase shifters, or delay lines are applied to the I or Q signal channel, then phase imbalance is compensated, but device complexity increases

Engineering Contradiction:

Improvephase imbalance compensation accuracyVSAvoidcalibration circuit complexity

Core Design Contradiction:

Measurement precisionVSDevice complexity

Solution Approach 1:

The patent replaces physical calibration components (asymmetric filters, variable phase shifters, delay lines) with a digital signal processing approach. The sampling clock delay adjustment and digital compensation algorithms substitute for complex analog calibration circuits, reducing hardware complexity while maintaining phase imbalance compensation accuracy.

Inventive Principle:

Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the sampling clock phase parameter to introduce a controllable delay that compensates for phase imbalance. By adjusting the sampling clock delay and applying digital compensation coefficients, the system achieves phase correction without adding complex calibration hardware.

Inventive Principle:

Principle #35Parameter changes

2Adaptability or versatility

If digital signal processor is used to estimate phase imbalance coefficients and digitally compensate, then calibration flexibility is improved, but processing time and computational complexity increase

Engineering Contradiction:

Improvecalibration flexibilityVSAvoidprocessing time

Core Design Contradiction:

Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent performs phase imbalance calibration during the manufacturing or initialization phase, storing the compensation coefficients in memory. This preliminary calibration action eliminates the need for real-time computational compensation during signal processing, reducing processing time while maintaining calibration flexibility through stored coefficient sets.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12381513B2IQ phase imbalance calibration using sampling clock delay adjustment

Publication Date: 2025.08.05 GLOBALFOUNDRIES US INC

AI summary

A system for phase imbalance calibration, including: an in-phase (I) signal channel including an analog-to-digital converter (ADC) for sampling an I signal to provide a sampled I signal; a quadrature (Q) signal channel including an ADC for sampling a Q signal to provide a sampled Q signal; a sampling clock for controlling the sampling of the ADC on the I signal channel and the sampling of the ADC on the Q signal channel; and sampling clock delay circuitry for adjusting one of a sampling start time of the ADC on the I channel and a sampling start time of the ADC on the Q channel relative to one another such that the sampled I signal and the sampled Q signal are in phase.