Angle Demodulation By Phase Difference Detection TRIZ Cases
- Automotive Radar Interference Cancellation Using Dual Receivers
Dual-receiver radar processing detects and subtracts mutual interference to preserve SNR and improve target detection in autonomous driving.
- PLL Interference Cancellation for Modulated Signal Jamming
PLL filters track, reconstruct, and subtract FSK, MSK, and CW interference to recover cleaner input signals under jamming.
- ADC Sampling Clock Delay for IQ Phase Imbalance Calibration
Adjusting ADC sampling clock delay aligns I and Q channels to correct phase imbalance and improve image rejection in wireless receivers.
- Crystal-Less CDR Frequency Detection for Stable Clock Recovery
Using data transition density as feedback, this case stabilizes crystal-less CDR clock frequency without an external reference.
- Clock Data Recovery Loop Filter With Phase Delay Compensation
A dual-path loop filter with negative-feedback compensation cuts phase-delay latency and shortens clock recovery lock time under jitter.
- Three-Level Slicer CDR for ISI-Resistant Logical Signal Detection
Three-point voltage and clock adaptation improve logical signal detection under parasitic-capacitance ISI, reducing recovery errors.
- SERDES Transceiver Bypass Channel for Low-Latency Data Transfer
A low-latency bypass channel cuts SERDES delay from multi-stage de-serialization while DLL clock alignment supports higher-rate transfer.
- Receiver Clock Adjustment for Multi-Receiver Frequency Drift
Per-receiver clock adjustment corrects crystal oscillator drift without degrading other receivers, keeping baseband data rates consistent.
- Multi-Phase Clock Switching Circuit for Glitch-Free Phase Handover
Voltage-level protection controls phase selection so multi-phase clock switching avoids glitches and keeps output signals continuous.
- Lock-In Amplifier Integration for Phase-Synchronous Signal Analysis
Combining phase-synchronous processing with a lock-in amplifier adds time-domain, frequency-domain, and multi-harmonic analysis in one instrument.
- Video PLL Locking for Multi-Standard Clock Jitter Reduction
Pre-measuring incoming video frequency lets the PLL set dividers and filters quickly, reducing jitter across NTSC and PAL streams.
- Receiver-Side Oversampling Circuitry for Jitter Tolerance
A data communications circuit uses receiver-side oversampling and downsampling to process incoming signals at the core data rate.
- Clock Data Restoration Device with Dynamic Sampling Timing
A clock data restoration device adjusts sampling phases to match peak data transition times for stable signal recovery.