Video PLL Locking for Multi-Standard Clock Jitter Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional video imaging systems experience significant clock jitter when attempting to lock onto the frequency of incoming video signals due to the need to determine and adjust for multiple possible video formats, leading to instability in the output clock signal.
Innovation Solution
A video detection circuit with a phase lock loop (PLL) system that includes a synchronization separator, frequency counter, decision logic circuit, 1/N divide circuit, phase comparator, low pass filter, and controlled oscillator, which quickly narrows the operation range to minimize jitter by determining the appropriate settings for the PLL based on the detected video frequency, using a look-up table or logic circuit to adjust divider and filter settings for rapid lock-on.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a conventional PLL system attempts to determine and lock to the appropriate video clock frequency from multiple possible formats, then the system can support multiple video formats (NTSC, PAL, etc.), but clock jitter occurs and the output clock signal becomes unstable
Solution Approach 1:
The patent applies preliminary action by using a frequency counter to measure the incoming video signal frequency before the PLL locking process begins. This pre-measurement allows the system to predict the correct PLL divider settings in advance, avoiding the jitter that occurs during frequency searching and format detection. The frequency counter provides advance information about the signal format, enabling the PLL to lock directly to the correct frequency without oscillation.
Solution Approach 2:
The patent replaces the conventional mechanical/analog frequency searching method with a digital frequency counter and microprocessor-based system. Instead of relying on the PLL to mechanically search through possible frequencies, the system uses digital frequency measurement to determine the exact frequency, then calculates the appropriate divider settings digitally. This substitution of digital measurement and calculation for analog frequency searching eliminates the jitter inherent in conventional PLL locking.
2Adaptability or versatility
If the PLL system searches for and locks onto the clock frequency of the incoming video signal, then the system can adapt to different video formats, but the spectral purity of the output clock signal deteriorates due to clock jitter
Solution Approach 1:
The frequency counter performs preliminary frequency measurement before the PLL locking process, allowing the system to determine the exact incoming frequency and calculate the appropriate divider settings in advance. This pre-determination eliminates the frequency searching process that causes spectral impurity, enabling the PLL to lock directly to the correct frequency without the oscillations that degrade spectral purity.
Solution Approach 2:
The system uses feedback by continuously monitoring the frequency counter measurements and using this information to adjust the PLL divider settings. The microprocessor reads the frequency counter, determines the video format, and configures the PLL parameters accordingly. This closed-loop feedback mechanism ensures that the PLL maintains optimal settings for the detected format, preserving spectral purity while adapting to different video standards.
3Measurement precision
If the receiving circuit attempts to determine the video format by comparing incoming signal to reference signals, then the system can identify the correct clock frequency, but the locking process takes time and causes significant jitter
Solution Approach 1:
The frequency counter performs preliminary frequency measurement immediately upon receiving the video signal, providing advance knowledge of the incoming frequency before the PLL locking process begins. This pre-measurement eliminates the time-consuming frequency searching and comparison process, allowing the system to configure the PLL with the correct divider settings from the start and lock almost immediately without the prolonged jitter period characteristic of conventional format detection.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution significantly reduces clock jitter during frequency locking, enabling faster and more stable processing of incoming video signals across various formats like NTSC and PAL, ensuring a stable output clock signal.
Implementation Method 1
a phase locked loop (PLL) system compares an incoming video signal to a reference signal and attempts to determine and lock to the appropriate video clock frequency and provide a stable output signal
Data Source
AI summary
A video processing system includes a video detection circuit for determining the clock frequency of an incoming video signal. Using the determined clock frequency, adjustments are made in a phase lock loop to enable a quick lock onto the clock frequency of the incoming video signal.