Clock Data Recovery Loop Filter With Phase Delay Compensation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing clock data recovery circuits face challenges in achieving high responsiveness due to increased latency in loop filters, which is exacerbated by the need for high accuracy in setting constant numbers, leading to circuit size increases and potential data reception failures in intermittent data transmission scenarios.
Innovation Solution
A clock data recovery circuit design incorporating a loop filter with a first path for phase adjustment, a second path for frequency tracking, and a compensator providing negative feedback to compensate for phase delay, allowing for high responsiveness and reduced latency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a loop filter is used to reduce phase delay, then phase synchronization stability is improved, but circuit latency increases and responsiveness deteriorates
Solution Approach 1:
The loop filter is divided into two separate paths: a first path for phase adjustment and a second path for frequency tracking. This segmentation allows each path to be optimized independently, enabling the phase path to respond quickly while the frequency path ensures long-term stability, thus resolving the contradiction between stability and responsiveness.
Solution Approach 2:
The invention introduces different gain parameters for the two paths: loop gain for the phase adjustment path and frequency tracking gain for the frequency tracking path. By changing and independently controlling these parameters, the system achieves high responsiveness in phase locking while maintaining stable frequency tracking, effectively resolving the latency-stability contradiction.
2Measurement precision
If constant numbers are set with high accuracy to compensate for loop filter latency, then phase delay compensation is improved, but circuit size increases
Solution Approach 1:
Instead of using complex constant number settings with high accuracy, the invention changes the approach by introducing adjustable gain parameters (loop gain and frequency tracking gain) that can be optimized without increasing circuit complexity. This parameter-based approach achieves effective compensation while avoiding the need for high-precision constant number settings that would increase circuit size.
3Measurement precision
If circuit size increases to achieve high accuracy constant number settings, then compensation precision is improved, but delay amount in circuit increases
Solution Approach 1:
The invention avoids increasing circuit size by changing from constant number settings to gain parameter optimization. The loop gain and frequency tracking gain can be adjusted to achieve high compensation precision without adding circuit complexity, thereby preventing additional delay that would result from a larger circuit.
4Reliability
If high responsiveness is required for intermittent data transmission, then data reception reliability is improved, but loop filter latency compensation becomes more difficult
Solution Approach 1:
By segmenting the loop filter into two independent paths with different functions, the invention achieves high responsiveness suitable for intermittent data transmission without requiring complex latency compensation mechanisms. The phase path provides quick response while the frequency path ensures reliability, simplifying the overall design.
Solution Approach 2:
The invention uses gain parameter optimization instead of complex latency compensation techniques. By adjusting the loop gain and frequency tracking gain, the system achieves high responsiveness for intermittent data reception without increasing loop filter complexity or requiring sophisticated compensation mechanisms.
Data Source
AI summary
In a clock data recovery circuit according to related art, it is difficult to achieve a high responsiveness. According to one embodiment, a clock data recovery circuit includes a loop filter, the loop filter including a first path (121, 122) that determines a loop gain that sets a speed of adjusting a phase of a recovery clock to a phase of an input signal, a second path (123, 124) that determines a frequency tracking gain that sets a speed of adjusting a frequency of the recovery clock to a frequency of the input signal, and a compensator 130 that gives a negative feedback from an output side to an input side of the first path and compensates for a phase delay of an output of a phase detector due to a delay amount of the loop filter.