Three-Level Slicer CDR for ISI-Resistant Logical Signal Detection
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Solution Overview
Problem
Existing logical signal transmission systems face challenges in accurately identifying and resolving logical signals due to parasitic capacitances that introduce inter-symbol interference, degrading signal integrity and increasing error probabilities.
Innovation Solution
A logical transmission system that includes a driver, a transmission line of characteristic impedance, a three-point three-level slicer, and a CDR circuit with a delay chain, resolution circuit, and DSP circuit to adapt reference voltages and clocks, improving signal resolution and accuracy through clock-data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional two-point two-level slicer is used for signal detection, then the device complexity is low, but the measurement precision and reliability of logical signal detection deteriorate due to inter-symbol interference from parasitic capacitances
Solution Approach 1:
The conventional two-point two-level slicer is segmented into a three-point three-level slicer that samples the received signal at three distinct voltage levels (high, mid, low) and three time points. This segmentation allows the system to distinguish between actual signal transitions and false transitions caused by parasitic capacitances, thereby improving detection accuracy while managing complexity through structured signal analysis
Solution Approach 2:
The invention adds temporal and voltage-level dimensions to the detection process by introducing mid-level voltage sampling and three-point time sampling. This dimensional expansion transforms the detection from a simple two-level comparison to a three-dimensional analysis space, enabling the system to resolve ambiguities caused by inter-symbol interference without excessive complexity increase
2Reliability
If reference voltages and clock timing are fixed, then the device complexity is low, but the reliability of signal recovery deteriorates under varying signal conditions
Solution Approach 1:
The system transitions from fixed reference voltages and clock timing to dynamic, adaptive parameters. The reference voltages are adjusted based on the detected signal distribution and the clock timing is optimized based on the recovered data patterns. This dynamic adaptation improves reliability under varying signal conditions while the complexity is managed through iterative optimization algorithms
Solution Approach 2:
The invention implements feedback loops where the three-point three-level slicer output feeds into a clock-data recovery circuit that continuously adjusts reference voltages and clock timing based on detection accuracy metrics. This feedback mechanism enables the system to self-optimize and maintain high reliability without requiring manual intervention or overly complex predetermined configurations
Data Source
AI summary
A logical transmission system includes a driver configured to receive a source data and output a first voltage at a first node; a transmission line of a characteristic impedance configured to couple the first node to a second node; a three-point three-level slicer configured to receive a second voltage at the second node and output a first ternary signal, a second ternary signal, and a third ternary in accordance with a first reference voltage, a second reference voltage, a first clock, a second clock, and a third clock; and a CDR (clock-data recovery) unit configured to receive a reference clock, the first ternary signal, the second ternary signal, and the third ternary signal and output a recovered data, the first reference voltage, the second reference voltage, the first clock, the second clock, and the third clock.