Clock Data Restoration Device with Dynamic Sampling Timing
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Solution Overview
Problem
Conventional clock data restoration devices struggle to reliably restore clock signals and data when transmitter clock jitter and intersymbol interference are significant, leading to instability in signal recovery.
Innovation Solution
A clock data restoration device comprising a sampler section, detection section, timing determination section, and clock output section, which adjusts the phases of clock signals to match the peak times of data transition distributions based on the differences between preceding bits, thereby stabilizing clock signal and data recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional clock data restoration devices use fixed sampling timings, then the device structure is simple, but the device cannot reliably restore clock signals and data when transmitter clock jitter and intersymbol interference are significant
Solution Approach 1:
The patent applies dynamics by making the sampling timings adjustable rather than fixed. The timing determination section dynamically calculates optimal sampling timings based on detected timing relations between clock signals and data transitions. This allows the system to adapt to varying clock jitter and intersymbol interference conditions, significantly improving restoration reliability under challenging signal conditions.
Solution Approach 2:
The patent implements feedback through the detection section that continuously monitors timing relations between clock signals and data transitions. The detected timing information is fed back to the timing determination section, which uses this information to calculate and adjust optimal sampling timings. This closed-loop feedback mechanism enables the system to compensate for clock jitter and intersymbol interference in real-time.
2Stability of the object's composition
If the device adjusts sampling timings to compensate for clock jitter and intersymbol interference, then restoration stability improves, but the device complexity increases
Solution Approach 1:
The patent segments the timing adjustment process into distinct functional sections: a detection section that identifies timing relations, a timing determination section that calculates optimal timings, and a sampler section that executes sampling. This segmentation allows each component to perform its specific function efficiently, managing overall system complexity while achieving stable signal recovery through coordinated operation of the segmented modules.
3Measurement precision
If the device uses multiple sampling timings to detect data transitions, then data detection accuracy improves, but the processing time and complexity increase
Solution Approach 1:
The patent applies preliminary action by having the detection section continuously monitor and detect timing relations between clock signals and data transitions in advance. This preliminary detection of timing patterns allows the timing determination section to pre-calculate optimal sampling timings before actual data recovery operations begin, improving detection precision while minimizing processing time during the actual data recovery phase.
Data Source
AI summary
With the clock data restoration device 1, as a result of the processing of a loop which comprises the sampler section 10, detection section 20, timing determination section 30, and clock output section 40, the respective phases of the clock signal CKXA, clock signal CKXB, and clock signal CK are adjusted to match the phase of the input digital signal, the digital signal sampling time indicated by the clock signal CKXA is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n−2) and value D(n−1) of the preceding two bits differ from one another, and the digital signal sampling time indicated by the clock signal CKXB is adjusted to match the peak time of the distribution of data transition times in a case where the value D (n−2) and value D(n−1) of the preceding two bits are equal to one another.