ADC Sample Clock DLL Layout for Lower Jitter
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Solution Overview
Problem
Conventional ADC systems with delay locked loops (DLLs) face challenges in maintaining sample clock jitter performance, especially at lower clock speeds, where the rising edge of the hold signal can occur before the sampling clock, leading to functional failures due to varying delays and limited clock speed compatibility.
Innovation Solution
The proposed ADC system incorporates a DLL with a variable delay line and a fixed delay circuit, reducing the number of inverters and buffers in the signal path, and using a clock generator to generate clock signals from taps on the delay line, ensuring a constant delay between the sampling clock and hold signal across frequencies, thereby improving jitter performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If a delay circuit is included to align edges, then edge alignment is achieved, but jitter is increased
Solution Approach 1:
The patent removes the delay circuit from the signal path while maintaining edge alignment through the DLL's phase adjustment capability. The DLL extracts only the necessary phase alignment function without the additional jitter-introducing delay stages, thereby resolving the contradiction between achieving edge alignment and minimizing jitter.
2Productivity
If DLL locks to full period clock signal, then clock signals are generated, but delay varies with clock frequency
Solution Approach 1:
The patent introduces a fixed delay circuit that provides a predetermined delay amount before the signal enters the variable delay line. This preliminary fixed delay establishes a baseline that, when combined with the DLL's variable delay adjustment, maintains consistent total delay across different clock frequencies. The fixed delay portion ensures that the overall delay remains stable regardless of frequency changes.
3Stability of the object's composition
If variable delay line is used for phase adjustment, then edge alignment is achieved, but delay changes with clock speed
Solution Approach 1:
The patent combines a fixed delay circuit with a variable delay line in series. The fixed delay provides a stable baseline delay that is independent of clock frequency, while the variable delay line provides the necessary phase adjustment capability. This merging of fixed and variable delay elements creates a hybrid system that maintains both phase alignment capability and clock speed compatibility.
Data Source
AI summary
In conventional analog-to-digital converter (ADC) systems, jitter can be a problem because of delay circuits within the sample signal path. Here, an ADC system is provided with a modified delay locked loop (DLL), namely having a variable delay and a fixed delay. The modification to the delay line of DLL enables the removal of delay circuits from the sample path, improve the overall signal to noise ration (SNR).