Analogue/Digital Conversion TRIZ Cases

Cross-coupled sensing and current-mode control speed low-side clamping while minimizing voltage offset across wide load currents.

Multi-phase sampling detects burst timing from data transitions, cutting lock time and reducing preamble overhead in serial links.

Parallel IF amplification and ADC paths preserve bit resolution across a wide operating range while enabling real-time signal measurement.

A hierarchical track-hold tree cuts power use and eases skew timing adjustment for high-frequency analog signal processing.

Two non-overlapping reversed-polarity transfer phases cancel comparator offset and delay errors, improving CBSC sampled-value accuracy.

Switched offset cancellation with an offset capacitor and zero-crossing timing improves sampled-data accuracy without continuous high power use.

A three-level half-bridge PWM stage holds ground during silent periods and rescales input gain to offset supply mismatch and avoid audio distortion.

A reduced-rate phase search samples at T±T/n to find the best correlation, cutting wireless receiver power and hardware cost.

Selective switching between p-type and n-type input pairs preserves rail-to-rail range while improving CMRR, PSRR, and noise behavior.

An RC network shifts a transfer-function zero to reduce sampling-instant dependence and harmonic distortion in high-speed ADC track-and-hold circuits.

A fixed-plus-variable DLL removes sample-path delay circuits to keep clock-to-hold timing stable and improve ADC jitter and SNR.

By subtracting rising and falling pulse-edge measurements, this differential ADC rejects low-frequency noise and improves touch charge accuracy.

Combining sparse sampling with Cadzow denoising reconstructs finite-rate-of-innovation signals below Nyquist while improving noise rejection.

By suspending the system clock during ADC critical phases, this case cuts mixed-signal noise coupling while preserving throughput in non-critical intervals.

Switching between Lagrange and zero-order interpolation by polarity reversal frequency reduces high-range distortion and aliasing noise.

Phase-shifted clock signals derive timer LSBs at lower clock frequency, cutting power use without sacrificing time resolution.

A capacitive feedback array and digital integrator make continuous-time sigma-delta modulation less sensitive to clock jitter and noise folding.

Dynamic element matching rearranges delay line elements in TDCs to reduce delay variation, improve linearity, and increase timing accuracy.

Asynchronous biphasic pulse coding replaces power-hungry A/D conversion and bounds spike rates to cut bandwidth and power.

Using a non-binary SAR DAC in power-on offset trim relaxes D/A matching demands and keeps amplifier compensation error within half an LSB.

Timed pulse transfer through a shared insulation transformer enables thermocouple disconnection detection while cutting component count, size, and cost.

Parallel delay paths with fractional offsets let this TDC resolve phase differences below one inverter delay and improve DPLL timing accuracy.

Iterative ADC clock adjustment detects desired DME signals across Nyquist bands while avoiding aliasing interference and analog channel selection.

Multiple analog signals are converted through one ADC by separating center frequencies and digitally recovering each channel, cutting size and cost.

Segmented resistor strings and interpolation amplification cut LCD driver DAC area while preserving high display resolution and color gradation.

A programmable buffer raises input impedance and adapts gain, chopping, and filtering to protect sensor accuracy across low-voltage ADC inputs.

Histogram-based thresholding and blanking reduce RF interference while preserving weak-signal data for more accurate extraction.

AC-coupled switch control and charge pumps let a differential sampler handle input common-mode voltages beyond supply rails with low noise.

Peak-to-average ratio estimation lets AGC hold ADC input peaks under RF interference, improving dynamic range use and interference detection.

Charge-pump-driven rectifying switches let ADC front ends sample bipolar differential signals beyond supply rails with lower noise and drift.

Current steering, push-pull action, and zero cancellation help a unity-gain ADC buffer keep linearity, stability, and bandwidth at low supply voltage.

Multiple delay paths with sub-inverter offsets and calibration improve TDC phase resolution for DPLLs while managing delay-path complexity.

Peak-to-average ratio lets receiver AGC hold ADC input range under narrowband RF interference, improving signal quality and detection accuracy.

A delay line and correction logic refine clock-edge interval sensing in memory cell converters, improving resolution without raising clock speed.

DMA transfers memory descriptors to the ADC controller so conversion sequences run without CPU intervention, cutting power use and raising throughput.

Oversampled SAR conversion aligns sample timing across multiple channels to cut phase delay, lower power use, and support fast measurements.

By splitting a full-bandwidth input into harmonic-mixed paths, this digitizer captures high-frequency signals with lower ADC rates, less noise, and lower complexity.

A single pre-amplifier handles multiple input signals through selection, offsetting, gain control, and buffering to cut circuit area and cost.

A single adder reused across MASH stages cuts accumulator area while preserving higher-order noise shaping performance.

Adaptive power inversion reshapes AGC input to prevent loop divergence from pulsed interference and preserve reliable radionavigation demodulation.

A single coded ruler and camera combine absolute position reading with fine interpolation, while dual-expansion rulers offset temperature and tilt.

Dual fast and slow gain reduction helps hearing amplifiers prevent ADC clipping while reducing pumping and switching noise.

Compressed sensing replaces uniform ADC sampling with linear projections to capture sparse wideband signals at lower data rates.

A shared reference-voltage ladder enables parallel ADC conversion with lower area, energy use, and fixed pattern noise in imaging detectors.

Error vector magnitude is used to estimate sample clock offset in a receiver, enabling fractional resampling for more accurate demodulation.

Capacitor-based offset sampling during charge transfer lets zero-crossing detectors preserve output accuracy in switched-capacitor circuits with lower power.

Phase-shifted sampling near carrier zero crossings captures I/Q information in one path, cutting demodulator hardware complexity and cost.

Digital gain thresholds trigger automatic switching between high- and low-sensitivity recording modes to keep audio levels balanced.

Estimating peak-to-average ratio from digital samples lets AGC hold ADC input magnitude and detect narrowband interference.

Phase-error-based delay control aligns samples to target sinusoidal phase angles without excitation signals, cutting processing time and memory use.