Unity-Gain Input Buffer Topology for Low-Voltage ADC Linearity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
High-speed analog-to-digital converters (ADCs) require integrated unity-gain input buffers that maintain high linearity, stability, and bandwidth while operating at low supply voltages, especially as sampling frequencies and input frequencies increase, to minimize noise and signal distortion.
Innovation Solution
A high-speed unity-gain input buffer design utilizing a configuration of NMOS and PMOS transistors, along with current sources and a compensation capacitor, which steers current through multiple paths to achieve push-pull action and follower action, enhancing linearity and stability, and allowing operation at low supply voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional unity-gain input buffer designs are used, then the buffer can operate at standard supply voltages, but the linearity and stability deteriorate at low supply voltages
Solution Approach 1:
The patent changes the operating parameters of the buffer by introducing a right-half plane zero cancellation mechanism and optimizing transistor sizing ratios. Specifically, the zero created by the feedforward path is cancelled by placing a zero in the left-half plane through feedback, allowing the buffer to maintain stability and linearity at low supply voltages where conventional designs fail
Solution Approach 2:
The patent employs feedback mechanisms to cancel the harmful right-half plane zero. By introducing a feedback path that creates an opposing zero in the left-half plane, the system compensates for the instability introduced by the feedforward path, enabling reliable operation at low supply voltages
2Speed
If high sampling frequency and high input frequency are used, then the bandwidth and drive capability increase, but the noise and signal distortion increase
Solution Approach 1:
The patent introduces an intermediate compensation network that acts as a mediator between the high-speed switching elements and the output. This network includes carefully designed RC time constants that filter out high-frequency noise and distortion components while preserving the desired signal bandwidth, effectively reducing harmful factors generated by high-frequency operation
3Power
If the buffer drives high capacitive loads at high speeds, then the drive capability improves, but the loop stability deteriorates due to right-half plane zeros
Solution Approach 1:
The patent converts the harmful effect of right-half plane zeros into a beneficial feature by deliberately introducing them through feedforward paths, then cancelling them using feedback. The right-half plane zero provides fast transient response, while its cancellation ensures stability, thus converting a potential harm into a benefit that enhances both speed and stability
Data Source
AI summary
A high-speed unity-gain input buffer steers the current that flows down a first path to an output node, and down a second path in response to an analog input signal. The current that flows down the second path is mirrored to sink a current out of the output node.