Memory Cell Sensing Converter With Delay-Line Resolution Correction
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Solution Overview
Problem
Existing analog to digital converters face challenges in accurately determining the duration of an input interval when its termination coincides with or is close to the active edge of a clock signal, leading to potential errors in resolution and measurement precision, particularly in memory cell sensing applications.
Innovation Solution
The implementation of a delay line and a controller forming a Delay Locked Loop configuration, which divides the clock period into increments to achieve higher resolution without increasing the clock frequency, and the use of flip-flops and decoders to determine the precise termination of the count within a single clock period, providing additional bits of resolution through a minimal amount of additional circuitry.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a delay line and controller forming a Delay Locked Loop configuration are implemented to divide the clock period into increments for higher resolution, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The clock period is segmented into multiple increments using a delay line with taps at different delay points. Each tap represents a discrete time increment, allowing the system to measure input interval duration with resolution finer than the original clock period. This segmentation enables high-resolution measurement without requiring a higher clock frequency.
Solution Approach 2:
A controller acts as an intermediary between the delay line and the measurement system. The controller selectively enables different delay line taps based on the measured duration, translating the continuous time measurement into discrete digital output values. This intermediary component coordinates the complex interaction between delay line, flip-flops, and decoder while adding minimal overall system complexity.
2Measurement precision
If flip-flops and decoders are used to determine precise termination of the count within a single clock period, then measurement precision is improved, but device complexity increases
Solution Approach 1:
Flip-flops are pre-configured to capture the state of delay line taps at specific moments during the counting process. By setting up the flip-flop configuration in advance and using the clock signal to trigger captures at precise intervals, the system determines termination points accurately without requiring complex real-time processing during the measurement interval.
Solution Approach 2:
The delay line creates multiple copies of the clock signal at different phase points (taps). Each tap represents a copied and delayed version of the original clock edge, allowing the system to check multiple time points simultaneously through parallel flip-flops and decoders. This copying approach enables precise termination detection by comparing against pre-established time markers.
3Measurement precision
If the clock frequency is increased to improve resolution, then measurement precision is improved, but use of energy increases
Solution Approach 1:
Instead of changing the clock frequency parameter, the system changes the temporal distribution parameter by introducing variable delays through the delay line. The effective resolution is improved by spreading the measurement across multiple delayed samples within the same clock period, rather than using a higher frequency clock. This parameter substitution maintains energy consumption at the original clock frequency while achieving finer measurement resolution.
Data Source
AI summary
A counter configuration operates in cooperation with a delay configuration such that the counter configuration counts an input interval based on a given clock speed and a given clock interval while the delay configuration provides an enhanced data output that is greater than what would otherwise be provided by the given clock speed. The counter configuration counts responsive to a selected edge in the clock interval. An apparatus in the form of a correction arrangement and an associated method are configured to monitor at least the delay configuration output for detecting a particular time relationship between an endpoint of the input interval and a nearest occurrence of the selected clock edge in the given clock signal that is indicative of at least a potential error in the enhanced data output and determining if the potential error is an actual error for subsequent use in correcting the enhanced data output.