Time-to-Digital Converter Using Offset Delay Paths for Fine Resolution
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Solution Overview
Problem
Conventional time-to-digital converters (TDCs) face limitations in achieving fine resolution due to the fixed delay of inverter paths, which restricts their performance in applications like digital phase-locked loops (DPLLs).
Innovation Solution
Implementing multiple delay paths with different time offsets of less than one inverter delay, along with a phase computation unit, to achieve a finer resolution than conventional TDCs, and calibrating the delay paths to ensure accurate timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If multiple delay paths with different time offsets are implemented, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The delay path is segmented into multiple parallel paths (first delay path, second delay path, etc.), each with different time offsets. This segmentation allows the system to measure phase differences with finer resolution by comparing signals across multiple time-shifted paths, thereby improving measurement precision while managing complexity through structured division.
Solution Approach 2:
The patent introduces a time offset dimension by creating delay paths with different time shifts (e.g., one half inverter delay apart). This adds a temporal dimension to the measurement process, enabling sub-inverter-delay resolution by exploiting the additional time dimension rather than simply increasing the number of inverters in a single path.
2Measurement precision
If calibration is performed to obtain accurate timing, then measurement precision is improved, but loss of time increases
Solution Approach 1:
Calibration is performed in advance to pre-determine the time offsets between delay paths. By conducting this calibration beforehand, the system establishes accurate timing relationships that can be reused during normal operation, improving measurement precision while minimizing the time loss impact since calibration is a one-time or periodic operation rather than a continuous overhead.
Data Source
AI summary
A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.