Power-On Amplifier Offset Trim With a Non-Binary SAR DAC

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Solution Overview

Problem

Current power-on calibration methods for operational amplifiers require extremely tight matching of D/A converter components, making them difficult to manufacture and leading to inaccuracies due to mismatch errors, especially with the MSB step size, which results in high production costs and time-consuming screening processes.

Innovation Solution

The use of a non-binary weighted D/A converter with a targeted bit ratio less than 2, allowing for more variation in component matching, reduces the stringent requirements and improves manufacturability by centering the error around zero, thereby reducing the maximum error from ±1 LSB to ±½ LSB.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If binary weighted D/A converter is used with successive approximation calibration, then offset compensation can be achieved, but extremely tight matching of D/A converter components is required making manufacturing difficult

Engineering Contradiction:
Improveoffset compensation accuracyVSAvoidD/A converter component matching
Core Design Contradiction:
Measurement precisionVSEase of manufacture

Solution Approach 1:

The patent changes the weighting parameter of the D/A converter from binary (powers of 2) to non-binary (specifically 1.618-based Fibonacci weighting). This parameter change allows relaxed matching requirements while maintaining calibration accuracy, as the less significant bits have smaller weights that tolerate component variation better.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The patent introduces asymmetric weighting where the ratio between consecutive bit weights is 1.618 rather than the symmetric binary ratio of 2.0. This asymmetric Fibonacci weighting scheme (where each weight is the sum of the two preceding weights) creates a more gradual distribution of significance across bits, reducing the stringent matching requirements on higher-order bits.

Inventive Principle:
Principle #4Asymmetry

2Manufacturing precision

If tight component matching is enforced to meet calibration specs, then manufacturing precision improves, but production time and costs increase

Engineering Contradiction:
Improvecomponent matching precisionVSAvoidproduction speed
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

By changing the D/A converter weighting parameter from binary to non-binary (Fibonacci-based), the patent reduces the required component matching precision. This allows standard manufacturing processes to produce components within relaxed tolerance ranges while still achieving the necessary calibration accuracy, thereby increasing production speed and reducing costs.

Inventive Principle:
Principle #35Parameter changes

3Ease of operation

If binary weighted D/A converter is used, then calibration can be performed, but MSB step size mismatch causes significant error

Engineering Contradiction:
Improvecalibration capabilityVSAvoidcalibration accuracy
Core Design Contradiction:
Ease of operationVSMeasurement precision

Solution Approach 1:

The patent changes the bit weighting parameter from binary (where MSB weight is twice the next bit) to non-binary Fibonacci weighting (where each bit weight is the sum of the two preceding weights with ratio 1.618). This parameter change reduces the MSB step size and distributes the calibration range more gradually, making the calibration process more robust to component mismatches and reducing significant error.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8102204B2Amplifiers with input offset trim and methods
Publication Date: 2012.01.24 NUMBER 14
  • US8102204B2 patent drawing
  • US8102204B2 patent drawing
  • US8102204B2 patent drawing

AI summary

Amplifiers with power-on trim and methods using an amplifier system having an amplifier system input and an amplifier system output, an amplifier, a comparator, a successive approximation register having an input coupled to an output of the comparator, a first switch for switching an input of the amplifier from the amplifier system input to shorting the amplifier input, a second switch for switching an output of the amplifier from the amplifier system output to an input of the comparator, an output of the successive approximation register being coupled to an N bit digital to analog (D/A) converter, the D/A converter being a non-binary converter using a radix of less than 2 for at least the most significant bits, and an output of the D/A converter being coupled to the amplifier to control the input offset of the amplifier. Novel embodiments for the amplifier, comparator and D/A converter are disclosed.