Mixed-Signal SoC Clock Gating for Low-Noise ADC Timing
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Solution Overview
Problem
Mixed-signal System-on-Chip (SOC) designs face significant challenges in reducing crosstalk and noise coupling due to high integration levels, which can lead to aberrant performance in high precision conversion circuits like ADCs, where noise corruption is exacerbated by electrical activity in interface and processing circuits.
Innovation Solution
Implementing a timing control mechanism that organizes operations into critical and non-critical phases, suspending the system clock during critical phases to minimize noise injection from other processing units, and allowing it to run freely during non-critical phases, using a time controller to manage the clock signals and distinguish between these phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the system clock is continuously supplied to all processing units, then overall system productivity is improved, but noise coupling and crosstalk increase during critical ADC conversion phases
Solution Approach 1:
The patent segments the operational timeline into critical phases (during ADC conversion) and non-critical phases (during interface circuit operation). The clock signal is selectively supplied only during non-critical phases and suspended during critical phases. This temporal segmentation allows the system to achieve both high ADC precision and acceptable overall throughput by optimizing clock distribution according to operational priorities.
2Object-affected harmful factors
If the system clock is suspended during critical phases, then noise coupling to ADC is reduced, but productivity of other processing units decreases
Solution Approach 1:
The patent implements periodic clock gating that rhythmically enables and disables the clock signal to processing units based on ADC conversion cycles. During each conversion cycle, the clock is gated off during critical phases and restored during non-critical phases. This periodic action ensures that noise-sensitive ADC operations receive uninterrupted clean signals while other processing units maintain acceptable throughput through regular clocked operation during non-critical intervals.
3Adaptability or versatility
If interface circuits operate simultaneously with ADC conversion, then system versatility is improved, but measurement precision of ADC deteriorates due to electrical activity noise
Solution Approach 1:
The patent segments operational timing into distinct critical and non-critical phases, allowing interface circuits to operate during non-critical phases when the clock is active, while ADC conversion proceeds uninterrupted during critical phases when the clock is gated. This temporal segmentation enables both functions to operate with high precision during their respective active periods, achieving both versatility and measurement accuracy.
Data Source
AI summary
An integrated circuit may include a plurality of circuit sub-systems that include at least one converter circuit operating in respective critical phases and non-critical phases of operation, a clock distribution circuit that has an input for an externally-supplied clock signal that is active during the non-critical phases and inactive during the critical phases, and a clock generator to generate an internal clock signal to the converter circuit that is active when the external-supplied clock signal is inactive.