Burst-Mode Clock Recovery Using Multi-Phase Sampling
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Solution Overview
Problem
In burst-mode communication systems, existing clock and data recovery circuits face challenges with lengthy initial locking times, which are undesirable due to reduced communication bandwidth and inefficiencies in using preambles for clock recovery, especially when multiple transmitters have independent amplitude and timing characteristics.
Innovation Solution
A clock and data recovery device with sampling, phasing, and selection circuitry that samples serial input signals at distinct time points to determine phase and select output data, allowing for near-instantaneous locking by identifying data transitions and utilizing this phase information to choose relevant samples, thereby reducing the need for lengthy preambles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional clock and data recovery circuits use preambles for clock recovery, then clock synchronization is achieved, but initial locking time increases and communication bandwidth is reduced
Solution Approach 1:
The patent extracts the clock recovery function from the data stream itself by detecting transitions in the received serial data, rather than relying on separate preamble sequences. The phase detector circuit identifies transitions in the sampled data to generate phase error signals, eliminating the need for dedicated preamble overhead while maintaining synchronization capability.
Solution Approach 2:
The received data signal serves multiple functions simultaneously: it carries both the information data and the clock timing information needed for synchronization. By detecting transitions in the data itself, the system uses the data stream for both communication and clock recovery purposes, eliminating the need for separate preamble sequences.
2Reliability
If lengthy preambles are used to allow for recovery of clock information, then clock recovery is more reliable, but communication bandwidth is unduly reduced
Solution Approach 1:
The patent extracts clock timing information directly from the data transitions themselves, removing the need for separate preamble sequences. The phase detector uses transition detection in the sampled data to generate synchronization signals, thereby eliminating preamble overhead while maintaining reliable clock recovery.
Solution Approach 2:
The system uses oversampling at multiple phases to ensure reliable transition detection without requiring lengthy preambles. By sampling at multiple time points within each bit period and detecting transitions among these samples, the system achieves robust clock recovery with minimal overhead.
3Adaptability or versatility
If multiple transmitters with independent amplitude and timing characteristics transmit data into the channel, then system flexibility is improved, but timing information from prior bursts becomes useless for subsequent bursts
Solution Approach 1:
The system performs preliminary transition detection within each burst to quickly establish synchronization. The phase detector circuit immediately begins detecting transitions in the sampled data at the start of each burst, enabling rapid locking without relying on timing information from previous bursts.
Solution Approach 2:
Each burst independently carries its own timing information through data transitions, allowing the receiver to self-synchronize to each burst without needing to maintain phase information from previous bursts. The transition detection mechanism extracts timing information directly from the incoming data stream of each burst.
Data Source
AI summary
A clock and data recovery device recovers data from a sequential stream of data that includes bursts of data separated by gaps. Each burst of data arrives with its own phase and with its own deviation from a nominal frequency. The bursts of data begin with a preamble that is utilized to determine the timing of the burst. The clock and data recovery device determines the timing of a burst of data using signals from one or more demultiplexers or samplers. At the start of each burst of data, sampled input signals are analyzed by an edge detector to determine a sample phase for the burst. A selector utilizes the sample phase determined by the edge detector to choose which of the sampled input signals to use to produce output data signals from the clock and data recovery device.