Sub-Inverter-Delay TDC Using Parallel Offset Delay Paths
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Solution Overview
Problem
Conventional time-to-digital converters (TDCs) face limitations in achieving fine resolution due to the fixed delay of inverter paths, which restricts their performance in applications like digital phase-locked loops (DPLLs).
Innovation Solution
Implementing multiple delay paths with different time offsets of less than one inverter delay, along with a phase computation unit, to achieve a finer resolution than conventional TDCs, and calibrating the delay paths to ensure accurate timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional TDC uses a single delay path with inverter stages, then the circuit structure is simple, but the resolution is limited to one inverter delay
Solution Approach 1:
The patent divides the single delay path into multiple parallel delay paths (first delay path with inverters 512a-512n, second delay path with inverters 514a-514n). Each path provides coarse phase difference measurement with one inverter delay resolution, while the combination of multiple paths enables fine phase difference measurement with sub-inverter-delay resolution through the delay unit and phase computation unit.
2Measurement precision
If the inverter delay is reduced to improve resolution, then the TDC resolution improves, but the delay unit cannot achieve delays less than one inverter delay
Solution Approach 1:
The patent adds a temporal dimension by introducing a delay unit that provides fractional delay (e.g., one half inverter delay) between the first reference signal and second reference signal. This temporal offset, combined with parallel delay paths, creates a multi-resolution measurement system where the fine phase difference can be determined by comparing outputs from multiple paths with different time offsets, achieving resolution better than one inverter delay.
3Measurement precision
If multiple delay paths are added to improve resolution, then the TDC resolution improves to less than one inverter delay, but the device complexity increases
Solution Approach 1:
The patent merges the outputs of multiple parallel delay paths through a phase computation unit that combines the coarse phase difference information from each path with the fractional delay information from the delay unit. This merging process synthesizes a fine phase difference measurement with resolution better than one inverter delay, achieving high precision without requiring each individual path to be excessively complex.
Data Source
AI summary
A time-to-digital converter (TDC) with fine resolution of less than one inverter delay is described. In an exemplary design, the TDC includes first and second delay paths, a delay unit, and a phase computation unit. The first delay path receives a first input signal and a first reference signal and provides a first output. The second delay path receives a second input signal and a second reference signal and provides a second output. The delay unit delays the second input signal relative to the first input signal or delays the second reference signal relative to the first reference signal, e.g., by one half inverter delay. The phase computation unit receives the first and second outputs and provides a phase difference between the input signal and the reference signal. Calibration may be performed to obtain accurate timing for the first and second delay paths.