Capacitive-Feedback Sigma-Delta Modulator for Clock Jitter Stability
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Solution Overview
Problem
Continuous-time sigma-delta modulators face performance limitations due to clock jitter, quantizer metastability, and non-linearity of the integrator, which lead to noise modulation and degradation in performance, especially at high frequencies and high bandwidths, and existing solutions like switched capacitors and multi-bit quantizers introduce additional issues such as limited bandwidth and power consumption.
Innovation Solution
A sigma-delta modulator design that uses a capacitive array with switch units connecting capacitors to either a first or second voltage level, controlled by a digital integrator to provide time-independent feedback, reducing jitter sensitivity and noise folding, and incorporating a digital integrator in the feedback path to maintain a stable noise transfer function.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If continuous-time sigma-delta modulator is used to achieve power efficiency and high input bandwidth, then power consumption is reduced and bandwidth is increased, but clock jitter causes noise modulation and performance degradation
Solution Approach 1:
The patent introduces an integrator as an intermediary component between the summing junction and the quantizer. This integrator accumulates the current over time, converting the time-dependent current signal into a voltage signal that is less sensitive to clock jitter. The integration process effectively filters out the high-frequency jitter noise while preserving the lower-frequency signal components, thereby maintaining performance stability in the continuous-time architecture.
2Measurement precision
If high sampling frequency is used to achieve noise performance benefits, then quantization noise is spread over wider frequency range, but implementation becomes impractically complex
Solution Approach 1:
The patent replaces the traditional discrete-time switching mechanism with a continuous-time integrator-based approach. Instead of using high-frequency switching and digital processing to achieve noise shaping, the system uses analog integration to naturally accumulate and smooth the quantization noise over time. This analog mechanism achieves similar noise performance benefits without requiring impractically high sampling frequencies or complex digital circuitry.
3Object-affected harmful factors
If multi-bit quantizer is used to reduce jitter sensitivity, then jitter sensitivity is reduced by factor of 2^N, but device complexity and power consumption increase
Solution Approach 1:
The patent segments the feedback current into multiple parallel paths, each corresponding to a different bit weight. Instead of using a single multi-bit quantizer that would require complex circuitry, the system divides the feedback into separate current mirrors or DAC channels, each handling a specific bit position. This segmentation allows the system to achieve jitter sensitivity reduction through the multi-bit feedback structure while keeping each individual quantizer element simpler and more manageable.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design achieves improved performance by making the feedback loop insensitive to clock jitter and reducing noise folding, while maintaining power efficiency and stability, with the ability to introduce intentional delay for additional regeneration or dynamic element matching.
Implementation Method 1
The sigma-delta modulator comprises a plurality of capacitive elements for smoothing the current flow, each capacitive element being connected at one end to the node and at its other end to a respective switch unit
Data Source
AI summary
A sigma-delta modulator for forming a digital output signal representative of a voltage level of an input signal, the sigma delta modulator having a node arranged to receive a current flow that is representative of the voltage level of the input signal and on whose voltage the digital output signal is dependent, the sigma-delta modulator comprising a plurality of capacitive elements for smoothing the current flow, each capacitive element being connected at one end to the node and at its other end to a respective switch unit and a plurality of switch units, each switch unit being arranged to connect the respective one of the capacitive elements to either a first voltage level or a second voltage level in dependence on the voltage at the node so as to provide feedback that affects the voltage at the node.