Receiver Sample Clock Offset Estimation Using Error Vector Magnitude

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Solution Overview

Problem

The challenge in accurately demodulating received baseband signals due to the offset between the actual and intended sample-clock-frequencies in digital signal processing systems, which leads to difficulties in recovering the original information bits.

Innovation Solution

A method involving an analog-to-digital converter capturing samples of a received baseband signal, followed by carrier-frequency and phase-offset removal, hard decision demodulation, and re-modulation to estimate the sample clock offset, allowing for fractional resampling to align the sample rate with the intended frequency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the receiver uses an actual sample-clock-frequency different from the intended frequency, then the receiver can operate with a different clock rate, but the demodulation accuracy deteriorates due to clock offset

Engineering Contradiction:
Improvesample clock frequency adaptabilityVSAvoiddemodulation accuracy
Core Design Contradiction:
Adaptability or versatilityVSMeasurement precision

Solution Approach 1:

The patent replaces traditional mechanical clock synchronization methods with a computational approach using Error Vector Magnitude (EVM) analysis. The system computes EVM values at different assumed clock frequencies and determines the optimal clock frequency through mathematical optimization rather than mechanical adjustment, thereby maintaining demodulation accuracy despite clock frequency variations.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Solution Approach 2:

The patent changes the operating parameter from fixed clock frequency to variable clock frequency with adaptive compensation. By calculating EVM across a range of clock frequency values and selecting the frequency that minimizes EVM, the system adapts to actual clock conditions while maintaining optimal demodulation performance, resolving the contradiction between clock flexibility and accuracy.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If traditional clock synchronization methods are used, then clock offset can be corrected, but the system complexity increases

Engineering Contradiction:
Improveclock offset correctionVSAvoidsynchronization system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent extracts the clock offset correction function from complex traditional synchronization systems and implements it through a simplified EVM-based computational method. By removing unnecessary synchronization components and retaining only the essential EVM calculation and optimization steps, the system achieves reliable clock offset correction with reduced complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The system performs self-diagnosis and self-correction by computing EVM values and automatically determining the optimal clock frequency without external intervention. The receiver independently identifies and corrects its own clock offset by selecting the clock frequency that minimizes EVM, eliminating the need for complex external synchronization infrastructure.

Inventive Principle:
Principle #25Self-service

3Measurement precision

If complex synchronization algorithms are implemented, then clock offset estimation accuracy improves, but the processing complexity and computational load increase

Engineering Contradiction:
Improveclock offset estimation accuracyVSAvoidprocessing algorithm complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent segments the clock offset estimation problem into discrete EVM calculations at different clock frequency hypotheses. Instead of using a single complex continuous optimization algorithm, the system divides the frequency range into discrete points, computes EVM at each point, and selects the optimal frequency, thereby reducing computational complexity while maintaining accuracy.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses a practical approximation by testing a limited set of discrete clock frequency values rather than exhaustively searching the entire frequency range. This partial action approach provides sufficient estimation accuracy for most applications while significantly reducing computational burden compared to exhaustive search methods.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS8654903B2Using error vector magnitude to estimate sample clock frequency offset
Publication Date: 2014.02.18 NATIONAL INSTRUMENTS CORP
  • US8654903B2 patent drawing
  • US8654903B2 patent drawing
  • US8654903B2 patent drawing

AI summary

A low complexity system and method for operating a receiver in order to estimate an offset between the actual sample clock rate 1/TS′ of a receiver and an intended sample clock rate 1/TS. The receiver captures samples of a received baseband signal at the rate 1/TS′, operates on the captured samples to generate an estimate for the clock rate offset, and fractionally resamples the captured samples using the clock rate offset. The resampled data represents an estimate of baseband symbols transmitted by the transmitter. The action of operating on the captured samples involves computing an error vector signal and then estimating the clock rate offset using the error vector signal. The error vector signal may be computed in different ways depending on whether or not carrier frequency offset and carrier phase offset are assumed to be present in the received baseband signal.