Comparator Offset Cancellation for Fast Sampled-Data Circuits
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Solution Overview
Problem
Operational amplifiers in sampled-data circuits face challenges in achieving sufficient open-loop gain, low noise, and fast settling times, especially with low power supply voltages and device gain limitations, which affect the accuracy and speed of signal integration in switched-capacitor circuits.
Innovation Solution
A comparator-based circuit with effective offset cancellation is introduced, utilizing a first amplifier, an offset capacitor, and control switches to connect the input terminal to a predetermined voltage, along with a noise averaging circuit to reduce power consumption without degrading noise performance or speed, using a zero-crossing detector to determine the precise moment for sampling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If operational amplifiers are used to provide sufficient open-loop gain and fast settling time, then signal integration accuracy is improved, but power consumption increases and device gain limitations are exacerbated
Solution Approach 1:
The patent implements periodic offset cancellation by switching the offset capacitor between different connection states at specific clock phases. During phase φ1, the offset capacitor is connected to cancel amplifier offset; during phase φ2, it is disconnected or reconfigured. This periodic action allows offset cancellation to occur only when necessary for accuracy, rather than continuously, thereby reducing power consumption while maintaining signal integration accuracy during critical sampling periods
Solution Approach 2:
The offset cancellation is performed in advance during the sampling phase before the actual signal integration and comparison occurs. By pre-cancelling the offset voltage on the offset capacitor during phase φ1, the amplifier is prepared in an optimized state before processing the signal during phase φ2, ensuring accuracy is achieved without requiring continuous high-power operation
2Speed
If operational amplifiers are designed for fast settling time, then sampling speed is improved, but achieving sufficient open-loop gain becomes more difficult under low power supply voltages
Solution Approach 1:
The patent segments the amplifier operation into distinct phases: offset cancellation phase and signal processing phase. During the offset cancellation phase, the amplifier operates with feedback to achieve precise offset nulling. During the signal processing phase, the pre-cancelled offset enables faster settling. This segmentation allows the amplifier to optimize for different performance requirements at different times, achieving both fast settling speed and sufficient effective gain
Solution Approach 2:
The offset capacitor serves as an intermediary element that stores and applies correction voltages to compensate for amplifier offset. By using this external compensation mechanism, the amplifier itself does not need to maintain excessively high open-loop gain continuously, allowing it to settle faster while still achieving accurate signal processing through the combined effect of the amplifier and offset capacitor
3Measurement precision
If offset cancellation is implemented continuously, then accuracy is maintained, but power consumption increases
Solution Approach 1:
The offset cancellation is performed periodically at specific clock phases (phase φ1) rather than continuously. The switch connected to the offset capacitor is closed during the offset cancellation phase to apply correction, then opened during the signal processing phase (phase φ2). This periodic operation maintains output voltage accuracy when needed while minimizing power consumption by disabling the cancellation mechanism during periods when it is not required
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables accurate and efficient offset cancellation in zero-crossing detectors, reducing power consumption while maintaining high accuracy and speed, suitable for applications in algorithmic and delta-sigma converters, and amplifiers.
Implementation Method 1
an offset capacitor to which a waveform generator is applied
Implementation Method 2
a waveform generator circuit, operatively connected to the offset capacitor, to apply a predetermined voltage waveform on the offset capacitor
Data Source
AI summary
A comparator based circuit with effective offset cancellation includes first and second amplifiers and an offset capacitor operatively connected to the first and second amplifiers. An offset voltage source generates an offset voltage. A first switch connects the offset voltage source to ground during a first time period. The first amplifier generates an output voltage in response to the first switch connecting the offset voltage source to ground during the first time period. A second switch connects the offset capacitor to ground during a second time period. The first switch disconnects the offset voltage source from ground during a third time period, and the second switch disconnects the offset capacitor from ground during the third time period.