Phase-Shifted Timer Circuit for Low-Power High-Resolution Counting

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

The power consumption of digital circuitry increases with higher clock frequencies, limiting the resolution and performance of timers in electronic devices, as the maximum power consumption occurs in least significant bit flip-flops, which are driven by the highest clock frequency.

Innovation Solution

An electronic device uses a counter driven by a clock signal with phase-shifted signals to derive least significant bits, allowing for a reduced clock frequency while maintaining time resolution, achieved through a clock generating stage with delay elements and a code converter stage that stores phase-shifted signals for efficient power usage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If the clock frequency is increased to improve timer resolution and performance, then the timer resolution is improved, but the power consumption increases

Engineering Contradiction:

Improvetimer resolutionVSAvoidpower consumption

Core Design Contradiction:

Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent segments the timer into two independent parts: a high-frequency counter for MSBs and a low-frequency phase-shifted clock system for LSBs. This segmentation allows each part to operate at its optimal frequency, with the LSB derivation requiring only 1/m of the original clock frequency, thereby reducing overall power consumption while maintaining timer resolution

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes the frequency parameter of the clock signal used for LSB derivation from the original high frequency f to a lower frequency f/m. By using phase-shifted clocks with m different phases, the system achieves the same time resolution with a reduced frequency, directly addressing the power consumption issue

Inventive Principle:

Principle #35Parameter changes

2Use of energy by moving object

If the clock frequency is reduced to decrease power consumption, then the power consumption is reduced, but the timer resolution deteriorates

Engineering Contradiction:

Improvepower consumptionVSAvoidtimer resolution

Core Design Contradiction:

Use of energy by moving objectVSMeasurement precision

Solution Approach 1:

The patent introduces a new dimension by using multiple phase-shifted clock signals (m different phases) instead of relying solely on increasing the frequency of a single clock signal. This dimensional approach allows the system to achieve fine time resolution through phase differentiation rather than frequency multiplication

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent introduces phase-shifted clock signals as an intermediary mechanism between the high-frequency counter and the final timer value. These intermediate signals with m different phases enable the derivation of LSBs at a lower frequency while preserving the required time resolution

Inventive Principle:

Principle #24Intermediary (Mediator)

Data Source

PatentUS8185774B2Timer for low-power and high-resolution with low bits derived from set of phase shifted clock signals

Publication Date: 2012.05.22 TEXAS INSTRUMENTS INC

AI summary

The present invention is an electronic device comprising a counter driven by an input clock signal for counting clock cycles and providing most significant bits of a count. A clock signal generating stage provides a first set of phase shifted clock signals having m different phases. The electronic device determines n least significant bits of the count of the counter from the logic states of the first set of m phase shifted clock signals.