Dynamic Element Matching in ADC/DAC Slices for Better Linearity
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Solution Overview
Problem
Analog to digital converters (ADCs) and digital to analog converters (DACs) face challenges in achieving high resolution and low integral non-linearity errors due to random variations during fabrication, leading to overweight or underweight elements that affect conversion accuracy and linearity.
Innovation Solution
A multistage ADC architecture is introduced, where elements are identified using counting schemes and a shuffling operation is applied to form a shared bit pattern, allowing for weighted contributions across slices, thereby increasing effective resolution and equalizing bit values between groups of elements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If dynamic element matching with shuffling operation is applied, then integral non-linearity errors are reduced and linearity is improved, but device complexity increases due to additional counting schemes and shuffling logic
Solution Approach 1:
The converter is divided into multiple slices, each containing a subset of elements. This segmentation allows independent identification and shuffling of elements within each slice using counting schemes, reducing the overall complexity compared to managing all elements in a single large array while still achieving global linearity improvement through coordinated shuffling across slices.
Solution Approach 2:
The element assignment to code positions is made dynamic through shuffling operations that vary the mapping between elements and codes based on identified patterns. This dynamic reassignment allows the system to adapt to fabrication variations and equalize bit values, improving linearity without requiring precise static matching of all elements.
2Measurement precision
If multiple slices with shuffling operation are used, then effective resolution is increased, but device complexity increases due to multiple counting schemes and coordination logic
Solution Approach 1:
The patent introduces a second dimension of organization by dividing elements into multiple slices with hierarchical indexing. The first counting scheme operates within slices while the second counting scheme operates across slices, creating a two-dimensional addressing structure that increases effective resolution without requiring a proportional increase in total element count.
Solution Approach 2:
The shuffling operation and counting schemes serve multiple functions: they identify element variations, equalize bit values across slices, and generate the final shuffled code output. This multi-functionality allows the same hardware logic to achieve both linearity improvement and resolution enhancement without requiring separate dedicated circuits for each function.
Data Source
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AI summary
The present disclosure provides a stage suitable for use in and ADC or a DAC where the stage comprises a plurality of slices that can be operated together to form a composite output having reduced thermal noise, while each slice on its own has sufficiently small capacitance to respond quickly to changes in digital codes applied to the slice. This allows a fast conversion to be achieved without loss of noise performance. The slices can be subdivided to reduce scaling mismatch between the most significant bit and the least significant bit. A novel shuffling scheme is implemented that allows shuffling to occur between the subsections of the slices without needing to implement a massively complex shuffler.