Analogue-Digital Converters TRIZ Cases

Remaining ADC channels raise sampling frequency and interpolate missing samples to sustain throughput after converter failure.

Memory cells with preset threshold voltages replace comparator banks to cut ADC area and power while preserving fast conversion.

Cantilevered disc springs center an encoder scale on the shaft, maintaining repeatable radial positioning despite shaft variation and temperature changes.

An on-chip oscillator and driver generate tunable calibration signals for time-interleaved ADCs, cutting external setup and bring-up time.

Multi-function touch driver pins switch between touch, sync, and GPIO roles to support more electrodes with lower driver size and cost.

Per-ADC sample tagging enables unit-specific correction of gain and offset errors, reducing TI ADC distortion and spurious output.

A non-tapered continuous wave signal narrows touch-panel bandwidth to reduce EMI and improve signal integrity in capacitive control.

Bypassing SPI and EMIF bottlenecks, N2HET and HTU capture ADC data to RAM without CPU intervention for faster, more reliable transfer.

Differential Ahuja compensation feeds the output back to both folded-cascode sides to stabilize negative loads and improve frequency response.

Reducing pre-stage supply current during ADC hold periods cuts circuit power use while preserving conversion accuracy.

Bit-scaled correlation calibrates time-interleaved ADC sampling skew, cutting correlation power and calibration time while preserving accuracy.

Internal timing circuitry lets the SAR ADC adapt to comparator delay, cutting fixed-clock wait time and power during conversion.

Coarse and fine delay control matches analog and ADC-DAC path timing in a continuous-time pipeline ADC, improving filter gain and stage resolution.

Measured latency and computed internal offsets synchronize chained ADC/DAC converters automatically, avoiding manual tuning and path-length constraints.

Dynamic coefficient calculation keeps phase and quadrature measurements accurate in metal detectors without synchronous sampling circuits.

Preloaded mode configuration and calibration data let an ADC switch operating modes without rebooting, cutting downtime and preserving stability.

A delay control element aligns the ADC-DAC path with the analog delay line, boosting filter gain, resolution, and PVT-tolerant tuning.

Random sub-ADC selection in an asynchronous TI-ADC turns mismatch errors into noise, reducing spurs and distortion without complex calibration.

Distortion correction circuitry models and cancels front-end distortion in transceivers, lowering BER at higher signal throughput.

Local processing in each radar unit cuts centralized load and synchronization complexity while scaling RF channels for better range and angle resolution.

Analog ADC sensing and timed standby cut powerline load monitor consumption below 10 mW without microprocessor overhead.

Frequency-modulated ultrasonic signals with time gating and FFT analysis improve object location accuracy and range despite sound-speed variation.

Asynchronous control advances noise-shaping conversion in a time-interleaved ADC to raise speed and signal-to-noise ratio with lower timing overhead.

Confidence map analysis flags defective 3D time-of-flight sensor pixels early, helping preserve measurement accuracy in autonomous vehicles.

A one-bit DAC plus analog low-pass filtering creates cleaner ADC training signals, improving non-linearity estimation and dynamic range.

Coarse-fine value splitting cuts A/D conversion power in analog MAC circuits while preserving accurate digital matrix-multiplication output.

A reference, high-pass filter, sampler, and buffer hold ADC common-mode voltage steady, supporting fast sub-ADC operation and accuracy.

Sampling rate follows signal energy across frequency bands, preserving analog signal quality while avoiding unnecessary power use.

An analog circuit enforces KKT conditions while a microcontroller programs the cost function, enabling real-time NLP solving with lower power.

A two-stage amplified capacitor ADC removes track-and-hold steps to raise sampling frequency while preserving fast, accurate conversion.

Scheduled control of clock and power intervals helps image sensors cut analog noise from digital circuits while lowering power use.

A proportional low-voltage reference circuit cuts inter-stage gain errors in pipeline ADCs, improving output accuracy, SNR, and harmonic distortion.

Fixed sampling-circuit parameter tuning corrects channel bandwidth mismatch in time-interleaved ADCs with less area and power.

Sampler reuse with multiple decoders speeds range profile capture while delaying quantization to cut switching noise and missed counts.

A coupled TX sample is processed digitally to cancel FDD leakage, easing duplexer isolation demands while protecting receiver sensitivity.

Balancing pulse delay passage times aligns overflow timing in dual delay circuits, reducing anomalous ADC code errors and improving accuracy.

Single memory-mapped entries configure analog blocks and signal channels, cutting programming overhead in compact mixed-signal ICs.

A sampling capacitor drives a controlled oscillator during readout, cutting ADC area and power while preserving conversion accuracy.

Bit-sum output and sign-bit processing prevent ADC overflow errors, improving conversion accuracy and resolution without slowing digitizing speed.

Distortion correction circuitry measures front-end distortion and applies cancellation functions to cut bit-error rates at higher signal throughput.

Two digitizations at different sampling frequencies remove harmonic aliasing and preserve over 60 dB instantaneous dynamics above 10 GHz.

A built-in test signal and shared multiplexed ADC path cut resolver and LVDT circuit complexity while preserving accurate, high-rate position sensing.

Collocated photodiodes and shared quantization let one pixel support 2D and 3D sensing with higher spatial resolution and lower power.

Slice-based shuffling and counting equalize element weights in ADCs and DACs, reducing integral non-linearity without a massive shuffler.

By scaling touch coordinates into reserved protocol bytes, this case enables sub-pixel touch accuracy without denser touchscreen hardware.

Dynamic ADC selection lets an image sensor vary readout paths, gain, and averaging to boost speed, dynamic range, and noise control.

Reused samplers, multiple decoders, and delayed quantization speed radar range digitization while reducing switching noise and missed counts.

Precomputed nested lookup tables let sub-ADC output vectors replace DSP processing, cutting ADC latency and complexity.

Calibration circuitry detects incomplete quantization and corrects output codes, helping pipeline ADCs stay accurate at higher clock speeds.

A dummy photodiode isolates leakage current so ADC subtraction can recover photon current and improve low-light sensing accuracy.