Interleaved ADC Common-Mode Stabilization for High-Speed Sampling
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Time-interleaved analog-to-digital converters face challenges in maintaining high-speed operation due to variations in input common mode voltage, which affects the performance of sub-ADCs.
Innovation Solution
The proposed analog-to-digital converter includes an interleaver with a reference circuit, high-pass filter, sampling circuit, and buffer, which processes the input signal to adjust the common mode voltage and ensure optimal operation of sub-ADCs, using a feed-forward scheme to maintain a fixed common mode voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If time-interleaved analog-to-digital converters use multiple sub-ADCs to achieve high sampling rate, then the sampling rate is improved, but the common mode voltage varies affecting sub-ADC performance
Solution Approach 1:
A common mode voltage generation circuit is introduced as an intermediary component between the power supply and sub-ADCs. This circuit generates a stable common mode voltage based on the power supply voltage, acting as a mediator that isolates the sub-ADCs from voltage variations caused by high-speed switching, thus maintaining reliable operation while enabling high sampling rates
Solution Approach 2:
The common mode voltage generation circuit dynamically adjusts the common mode voltage parameter based on the power supply voltage. By changing the common mode voltage parameter in response to power supply variations, the circuit ensures that sub-ADCs receive a stable reference voltage level, resolving the contradiction between high-speed operation and voltage stability
2Speed
If a fixed input common mode voltage is required for high-speed operation of sub-ADC, then the high-speed operation is improved, but the adaptability to varying input conditions deteriorates
Solution Approach 1:
The common mode voltage generation circuit automatically adjusts the common mode voltage based on the power supply voltage without requiring external intervention. This self-service mechanism ensures that the sub-ADCs always receive the appropriate common mode voltage for high-speed operation, while the system adapts to varying power supply conditions, thus maintaining both speed and adaptability
Data Source
AI summary
An analog-to-digital converter is provided. An analog-to-digital converter comprises an interleaver receiving and processing an input signal that is an analog signal and a plurality of sub-ADCs, wherein the interleaver includes a reference circuit outputting a second voltage based on a first voltage, a high-pass filter receiving the second voltage and outputting a first signal obtained by changing a common mode voltage of the input signal to the second voltage, a sampling circuit generating a second signal obtained by sampling an alternate current component of the first signal, and a buffer outputting a third signal obtained by buffering the second signal by using a buffering circuit, and the sub-ADC converts the third signal into a digital signal by using the first voltage.