Time-Interleaved ADC Calibration for Bandwidth Mismatch

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Solution Overview

Problem

Existing time-interleaved analog-to-digital converters face challenges in calibrating bandwidth mismatch between channels, requiring complex calibration mechanisms that increase circuit area and power consumption, particularly due to dependency on input signal frequency for compensation parameters.

Innovation Solution

A time-interleaved analog-to-digital converter system with a calibration circuit that adjusts control signals to optimize circuit parameters of sampling circuits, reducing bandwidth mismatch by iteratively determining and selecting the best parameter settings based on performance indicators, thereby reducing dependency on input signal frequency for calibration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If complex calibration mechanisms are used to calibrate bandwidth mismatch, then calibration accuracy is improved, but circuit area and power consumption increase significantly

Engineering Contradiction:
Improvebandwidth mismatch calibration accuracyVSAvoidcalibration mechanism complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent changes the parameter being calibrated from frequency-dependent correction parameters to fixed circuit parameters (such as capacitor values or resistor values) that directly affect bandwidth. By adjusting these physical parameters during calibration, the system achieves bandwidth mismatch correction without requiring complex frequency-dependent processing mechanisms, thereby reducing circuit area and power consumption while maintaining calibration accuracy.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If complex calibration mechanisms with frequency-dependent correction parameters are used, then bandwidth mismatch calibration is improved, but power consumption increases

Engineering Contradiction:
Improvebandwidth mismatch calibration accuracyVSAvoidpower consumption
Core Design Contradiction:
Measurement precisionVSUse of energy by moving object

Solution Approach 1:

The patent performs bandwidth mismatch calibration during an initial calibration phase before normal operation. By pre-determining and storing the optimal fixed parameters (such as capacitor ratios or resistor values) that compensate for bandwidth mismatch, the system eliminates the need for continuous frequency-dependent correction during signal processing. This preliminary calibration action significantly reduces power consumption during operational phases while maintaining accurate bandwidth matching.

Inventive Principle:
Principle #10Preliminary action

3Measurement precision

If complex calibration mechanisms are implemented, then bandwidth mismatch calibration is improved, but circuit area increases

Engineering Contradiction:
Improvebandwidth mismatch calibration accuracyVSAvoidcircuit area
Core Design Contradiction:
Measurement precisionVSArea of stationary object

Solution Approach 1:

The patent extracts and removes the frequency-dependent correction processing logic from the calibration mechanism. Instead of implementing complex adaptive algorithms that require additional processors, memory, and control logic, the solution extracts only the essential fixed parameters needed for bandwidth correction. This simplification dramatically reduces circuit area while maintaining the ability to calibrate bandwidth mismatch effectively.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS20240429933A1Time interleaved analog to digital converter and signal conversion method
Publication Date: 2024.12.26 REALTEK SEMICON CORP
  • US20240429933A1 patent drawing
  • US20240429933A1 patent drawing
  • US20240429933A1 patent drawing

AI summary

A time-interleaved analog-to-digital converter includes a plurality of sampling circuits, a plurality of analog-to-digital converter circuits, an output circuit, and a calibration circuit. The plurality of sampling circuits are configured to sequentially sample an input signal to generate a plurality of first signals, in which a circuit parameter of each of the plurality of sampling circuits is set according to a corresponding control signal in a plurality of control signals. The plurality of analog-to-digital converter circuits are configured to generate a plurality of first digital codes according to the plurality of first signals. The output circuit is configured to output a second digital code according to the plurality of first digital codes. The calibration circuit is configured to generate the plurality of control signals and adjust the plurality of control signals according to the second digital code.