Time-Interleaved ADC Reconfiguration After Channel Failure
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Solution Overview
Problem
Time-interleaved analogue-to-digital converters (ADCs) can become non-functional due to component aging, environmental stress, or failure, leading to compromised digital outputs and reduced throughput.
Innovation Solution
A time-interleaved ADC configuration that operates in both operational and compensation modes, where in compensation mode, the sampling frequencies of functional ADCs are increased to maintain overall sampling rate, and in data-interpolation mode, missing data is estimated by interpolating from adjacent functional ADC outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple ADCs are arranged in parallel for time-interleaved operation, then throughput is improved, but reliability deteriorates because the system becomes vulnerable to individual ADC failures
Solution Approach 1:
The patent dynamically changes the operating parameters (sampling frequencies) of the remaining functional ADCs when a failure is detected. By increasing the sampling frequencies of operational ADCs, the system compensates for the lost throughput capacity while maintaining the overall sampling rate, thus resolving the contradiction between throughput and reliability
Solution Approach 2:
The system transitions from a static parallel configuration to a dynamic reconfigurable architecture. When an ADC fails, the system dynamically adjusts the sampling frequencies of remaining ADCs and reinterleaves their outputs to maintain throughput, making the system adaptable to failure conditions while preserving reliability
2Productivity
If sampling frequency of individual ADCs is increased to compensate for failures, then throughput is maintained, but measurement precision deteriorates due to higher sampling rates beyond optimal ranges
Solution Approach 1:
The patent carefully adjusts sampling frequencies within optimal ranges rather than simply maximizing them. The controller selects new sampling frequencies that maintain throughput while staying within the accurate operating range of each ADC, preventing degradation of measurement precision
Solution Approach 2:
The system incorporates monitoring of ADC performance and failure detection mechanisms. This feedback allows the controller to make informed adjustments to sampling frequencies, ensuring that throughput compensation does not push ADCs into non-optimal operating regions where precision would deteriorate
3Reliability
If backup ADCs are added to replace failed units, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent enables the existing ADCs to serve multiple functions - they not only perform their primary conversion function but also dynamically adjust their sampling rates to compensate for failures in other ADCs. This self-service capability eliminates the need for dedicated backup ADCs, maintaining reliability without increasing complexity
Solution Approach 2:
Each ADC in the system is designed to be universally applicable and flexible in its operation. They can operate at different sampling frequencies and can take on increased workload when other ADCs fail, making the system more versatile without requiring specialized backup components
Data Source
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AI summary
A time-interleaved analogue-to-digital converter (1) including a first analogue-to-digital converter (2a), a second analogue-to-digital converter (2b), and a third analogue-to-digital converter (2c), each arranged to sample an analogue input (4) and produce a respective digital output (8a, 8b, 8c) based on the sampled analogue input (4), and also including a signal interleaving portion (10), arranged to combine the digital outputs (8a, 8b, 8c) from the analogue-to-digital converters to produce a digital output signal (14). The time-interleaved analogue-to-digital converter (1) is configured for operation both in an operational mode, and in a compensation mode when the third analogue-to-digital (2c) converter is non-functional. In the operational mode, the first and second analogue-to-digital converter (2a, 2b) sample the analogue input (4) respectively at a first frequency and a second frequency. In the compensation mode, the first and second analogue-to-digital converter (2a, 2b) sample the analogue input (4) respectively at a third frequency and a fourth frequency. The third frequency is higher than the first frequency, and the fourth frequency is higher than the second frequency.