Memory-Threshold ADC Architecture for Low-Power High-Speed Conversion
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Solution Overview
Problem
Conventional Flash ADCs face challenges with high power consumption, large chip area, and limited resolution, making them unsuitable for low-power and compact applications, while SAR ADCs suffer from similar issues of occupying a large circuit area and consuming significant power.
Innovation Solution
An ADC is designed using an array structure of memory devices with different threshold voltages, allowing for a compact and low-power implementation by converting analog signals into digital codes through bit detection units with state level determination modules and output modules, capable of generating thermometer codes and binary codes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional Flash ADC structure with comparator bank is used, then high speed conversion is achieved, but power consumption increases exponentially with resolution
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage comparison to threshold voltage matching. By using memory devices with predetermined threshold voltages that correspond to digital code levels, the ADC determines the digital output by comparing the analog input voltage against these threshold levels, rather than using traditional comparator banks. This parameter change enables low-power operation while maintaining high conversion speed.
Solution Approach 2:
The patent replaces the mechanical/electronic comparator system with a memory-based threshold voltage system. Instead of using active comparators that consume significant power, the invention uses memory devices (such as flash memory cells) whose threshold voltages are programmed during manufacturing to represent specific digital code levels. This substitution eliminates the need for power-hungry comparator circuits while preserving the high-speed conversion capability.
2Speed
If conventional Flash ADC structure with comparator bank is used, then high speed conversion is achieved, but chip area increases with resolution
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage comparison to threshold voltage matching. By using memory devices with predetermined threshold voltages that correspond to digital code levels, the ADC determines the digital output by comparing the analog input voltage against these threshold levels, rather than using traditional comparator banks. This parameter change enables low-power operation while maintaining high conversion speed.
Solution Approach 2:
The patent replaces the mechanical/electronic comparator system with a memory-based threshold voltage system. Instead of using active comparators that consume significant power, the invention uses memory devices (such as flash memory cells) whose threshold voltages are programmed during manufacturing to represent specific digital code levels. This substitution eliminates the need for power-hungry comparator circuits while preserving the high-speed conversion capability.
3Measurement precision
If number of comparators is increased to improve resolution, then measurement precision improves, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent makes the memory devices serve multiple functions: they store threshold voltage information during normal operation and simultaneously perform the analog-to-digital conversion function. Each memory device's threshold voltage acts as a reference level for comparison, eliminating the need for separate comparator circuits. This multi-functionality approach reduces circuit complexity while maintaining high resolution capability.
Solution Approach 2:
The patent uses copies of the same memory device structure with different threshold voltages to achieve high resolution. Instead of using different types of components (comparators, resistors, capacitors) with increasing complexity, the invention creates multiple instances of the same memory device type, each programmed with a specific threshold voltage during manufacturing. This copying approach maintains uniformity and simplifies the overall circuit design.
4Speed
If conventional Flash ADC structure is used, then high speed conversion is achieved, but the structure becomes difficult to use in low-power and compact applications
Solution Approach 1:
The patent changes the fundamental operating parameter from voltage comparison to threshold voltage matching. By using memory devices with predetermined threshold voltages that correspond to digital code levels, the ADC determines the digital output by comparing the analog input voltage against these threshold levels, rather than using traditional comparator banks. This parameter change enables low-power operation while maintaining high conversion speed.
Solution Approach 2:
The patent replaces the mechanical/electronic comparator system with a memory-based threshold voltage system. Instead of using active comparators that consume significant power, the invention uses memory devices (such as flash memory cells) whose threshold voltages are programmed during manufacturing to represent specific digital code levels. This substitution eliminates the need for power-hungry comparator circuits while preserving the high-speed conversion capability.
Data Source
AI summary
Provided is an analog-to-digital converter. The ADC includes a plurality of bit detection units. Each of the bit detection unit comprises: a state level determination module including a semiconductor device with a preset threshold voltage to receive an input signal; and an output module connected to the state level determination module and configured to detect and output a binary value corresponding to the input voltage. The bit detection units are configured to match one-to-one with the bits constituting a digital code, respectively. The state level determination module is configured to have a threshold voltage or conductance determined according to the bit of the digital code matched to the bit detection unit. Each of the bit detection units detects and outputs a binary value corresponding to the matched bit of the digital code from the input signal.


