One-Bit DAC Training for Accurate ADC Non-Linearity Modeling

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Solution Overview

Problem

In analog-to-digital converters (ADCs), non-linear impairments limit the dynamic range, and existing methods for characterizing these impairments are inaccurate due to the involvement of multi-bit digital-to-analog converters (DACs) that introduce additional non-linearities, leading to degraded performance and reduced dynamic range.

Innovation Solution

A system using a one-bit DAC and an analog low-pass filter generates a training signal, allowing the ADC linearizer to characterize non-linear impairments with relative accuracy by treating the combination of the one-bit DAC and ADC as a linear channel, employing either analytical methods or machine learning applications like neural networks to model and correct non-linearities.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If multi-bit DACs are used to generate training signals for ADC characterization, then the ADC can be driven with higher amplitude signals, but the multi-bit DAC introduces additional non-linearities that degrade measurement precision

Engineering Contradiction:
ImproveADC non-linearity characterization accuracyVSAvoidDAC non-linearities
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent replaces the complex multi-bit DAC with a simple one-bit DAC for training signal generation. The one-bit DAC is much simpler, cheaper, and introduces minimal non-linearities compared to multi-bit DACs. This disposable-like approach uses a basic component (one-bit DAC) that can be easily replaced or calibrated, sacrificing the complexity of multi-bit DACs to achieve cleaner training signals for ADC characterization.

Inventive Principle:
Principle #27Cheap short-living objects (Disposable)

Solution Approach 2:

The patent changes the resolution parameter of the DAC from multi-bit to one-bit. This parameter change fundamentally alters the training signal generation process, transforming it from a complex multi-level signal to a simple bipolar signal that passes through an analog low-pass filter. This parameter change eliminates the primary source of measurement error (DAC non-linearities) while maintaining the ability to characterize ADC performance accurately.

Inventive Principle:
Principle #35Parameter changes

2Measurement precision

If complex calibration hardware is used to characterize ADC non-linearities, then measurement precision improves, but device complexity and cost increase

Engineering Contradiction:
ImproveNon-linearity measurement accuracyVSAvoidCalibration hardware requirements
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent extracts and removes the complex multi-bit DAC from the training signal generation path, replacing it with a simple one-bit DAC and analog low-pass filter combination. This extraction eliminates the need for complex calibration hardware while maintaining measurement precision, as the simplified signal path introduces fewer error sources that would require additional hardware to compensate for.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent creates a simplified model of the training signal generator using a one-bit DAC that can be precisely characterized. This simple model serves as a clean reference that doesn't require complex calibration hardware, allowing the ADC non-linearities to be measured directly without the interference of complex DAC behavior that would require additional calibration equipment.

Inventive Principle:
Principle #26Copying

3Reliability

If high dynamic range is required for 5G applications, then signal quality improves, but non-linear impairments become more significant and harder to characterize accurately

Engineering Contradiction:
ImproveDynamic range performanceVSAvoidNon-linearity characterization accuracy
Core Design Contradiction:
ReliabilityVSMeasurement precision

Solution Approach 1:

The patent converts the limitation of the one-bit DAC (low resolution) into a benefit by using it to generate training signals with known, simple characteristics. The simplicity of the one-bit DAC output, when filtered through an analog low-pass filter, creates a clean training signal that accurately reveals ADC non-linearities without introducing the complex errors that would mask these measurements at high dynamic ranges.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively increases the dynamic range of ADCs by accurately modeling and correcting non-linear impairments, reducing quantization errors and improving the effective number of bits processed, while potentially reducing calibration hardware needs and operational costs.

Implementation Method 1

an analog low-pass filter configured to filter the DAC output signal to form the ADC input signal

Methodology Applied
Scientific EffectFiltering: Filter (electronic)

Data Source

PatentUS20250096810A1Analog-to-Digital Converter Non-Linearity Model Estimation Using Single-Bit Digital-to-Analog Converter
Publication Date: 2025.03.20 QUALCOMM INC
  • US20250096810A1 patent drawing
  • US20250096810A1 patent drawing
  • US20250096810A1 patent drawing

AI summary

A training signal generator for forming an input signal for an ADC-under-test includes a one-bit DAC and an analog low-pass filter. The one-bit DAC converts a binary sequence into a DAC output signal that is then filtered by the analog low-pass filter to form an ADC input signal. The ADC-under-test converts the ADC input signal into an ADC output signal. A digital low-pass filter converts the binary sequence into a plurality of samples. A digital signal processing system processes the plurality of samples and the ADC output signal to form an estimate of the ADC input signal. An ADC linearizer may then be trained to characterize a non-linear impairment of the ADC-under-test responsive to a comparison of the estimate of the ADC input signal and the ADC output signal.