Asynchronous SAR ADC Timing Circuit for Comparator Delay Control
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Solution Overview
Problem
The speed of operations in asynchronous analog-to-digital converters (ADCs) is limited by comparison delays, SAR logic delays, and variations in delay-generating elements, leading to unnecessarily long delays and increased power consumption.
Innovation Solution
The integrated circuit includes a comparator with an enable signal input and output, along with timing circuitry that utilizes transistors and inverters to control the enable signal and reduce operational delays, allowing for asynchronous operation with internal and variable duration control of SAR sequencing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If synchronous timing with fixed clock is used, then operation speed is limited by worst-case delay, but timing control is simple
Solution Approach 1:
The patent implements dynamic timing control where the SAR loop operates asynchronously without a fixed clock. The timing of comparison operations adapts to the actual delay characteristics of the comparator and SAR logic, allowing each operation to complete at its natural pace rather than being constrained by a worst-case fixed period. This dynamic approach eliminates unnecessary waiting time and achieves faster overall conversion speed.
2Measurement precision
If longer comparison delay is used, then measurement precision is improved, but operation speed decreases
Solution Approach 1:
The patent applies preliminary action by pre-charging the comparator inputs and preparing the SAR logic before each comparison operation. This ensures that when the comparison begins, all components are in their optimal initial states, allowing for accurate measurements without requiring excessively long comparison periods. The preliminary preparation enables both high precision and fast operation.
3Device complexity
If fixed clock timing is used, then device complexity is reduced, but power consumption increases due to unnecessary delays
Solution Approach 1:
The patent employs periodic action through the asynchronous nature of the SAR loop, where comparison operations are triggered only when needed rather than continuously by a fixed clock. Each comparison operation occurs periodically based on the completion of the previous operation, allowing the circuit to remain in a low-power state during idle periods while maintaining the ability to perform rapid conversions when required.
Data Source
AI summary
An integrated circuit including a comparator having an enable signal input and an output and timing circuitry. The timing circuitry includes a first transistor having a control terminal, a second transistor having a control terminal, a first inverter having an input coupled to the control terminal of the second transistor and having an output coupled to the enable signal input, and a second inverter having an input coupled to the output of the comparator and having an output coupled to the control terminal of the first transistor.