ADC Delay Circuit Balancing for Overflow Timing Accuracy
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Solution Overview
Problem
Existing analog-to-digital converter circuits face accuracy issues due to differences in overflow frequencies between first and second pulse delay circuits, leading to anomalous code errors and reduced conversion accuracy.
Innovation Solution
The proposed analog-to-digital converter circuit adjusts the passage times of pulse signals through first and second pulse delay circuits to match their turnaround times, using adjusters to equalize the delay times and reduce overflow frequency differences, thereby enhancing conversion accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If the first and second pulse delay circuits use the same number of delay units, then the circuit structure is simple and easy to manufacture, but the turnaround times differ causing overflow frequency mismatch and accuracy degradation
Solution Approach 1:
The patent changes the parameter of delay unit count from identical to different between first and second pulse delay circuits. Specifically, the first pulse delay circuit uses 2n-1 delay units while the second uses 2n+1 delay units, where n is a positive integer. This parameter change equalizes the turnaround times (T1 and T2) of both circuits, synchronizing their overflow frequencies and eliminating the accuracy degradation caused by timing mismatches.
2Measurement precision
If the passage times are made different to equalize turnaround times, then the overflow frequencies are synchronized improving accuracy, but the circuit design becomes more complex
Solution Approach 1:
The patent applies local quality by making specific delay units have different characteristics. The first pulse delay circuit contains a first delay unit with a first passage time, while the second pulse delay circuit contains a second delay unit with a second passage time. This localized differentiation in delay unit properties allows the overall turnaround times to be equalized without requiring complete redesign of the entire circuit architecture.
Solution Approach 2:
The patent introduces adjusters that can dynamically adjust the passage times of delay units. The first adjuster adjusts the first passage time and the second adjuster adjusts the second passage time, allowing dynamic equalization of turnaround times. This dynamic adjustment capability provides flexibility in optimizing the circuit for different operating conditions while maintaining accuracy.
Data Source
AI summary
In an A/D converter circuit, time required for a first pulse signal to have passed through all first delay units of a first pulse delay circuit is defined as first turnaround time, and time required for a second pulse signal to have passed through all second delay units of a second pulse delay circuit is defined as second turnaround time. Average time required for the first pulse signal to pass through any of the first delay units is defined as first passage time, and average time required for the second pulse signal to pass through any of the second delay units is defined as second passage time. A difference between the first and second passage times enables a difference between the first and second turnaround times to be smaller as compared with a reference difference therebetween for a case where the first and second passage times are identical to each other.