Asynchronous Time-Interleaved ADC for Faster Noise-Shaping Conversion
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Solution Overview
Problem
Existing analog to digital converters face challenges in achieving high-speed performance due to increased requirements for switching speed and power consumption, especially in high-speed applications.
Innovation Solution
A time-interleaved analog to digital converter with an asynchronous control mechanism, comprising multiple capacitor array circuits, transfer circuits, fine converter circuitry, and an encoder circuit, which performs noise shaping signal conversion and asynchronous control to improve processing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the operating speed of analog to digital converter is increased, then the conversion speed is improved, but the requirements for switching speed and power consumption increase making implementation more difficult
Solution Approach 1:
The analog-to-digital conversion process is divided into two independent parallel channels: a first capacitor array circuit for coarse conversion and a second capacitor array circuit for fine conversion. Each channel operates independently with its own sampling and conversion circuits, allowing the overall system to achieve high conversion speed without requiring a single complex high-speed circuit to handle the entire conversion process.
Solution Approach 2:
The patent employs an asynchronous control mechanism where the start time of noise shaping signal conversion is dynamically adjusted based on the completion status of coarse conversion. The control circuit selectively brings forward the start time of fine conversion when the first capacitor array circuit completes its operation early, optimizing the timing coordination between parallel channels to achieve high-speed conversion without fixed rigid timing constraints.
2Speed
If the operating speed of analog to digital converter is increased, then the conversion speed is improved, but the power consumption increases
Solution Approach 1:
The conversion process is segmented into coarse and fine conversion stages operating in parallel. Each stage uses dedicated capacitor arrays and control circuits that can be independently optimized for power efficiency. This segmentation allows the system to achieve high conversion speeds without requiring all circuits to operate at maximum power simultaneously.
Solution Approach 2:
The coarse conversion is performed first to establish a preliminary digital representation of the input signal. This preliminary action allows the fine conversion circuit to operate on a reduced dynamic range, thereby reducing its power consumption requirements while maintaining overall high conversion speed through the parallel architecture.
3Ease of operation
If synchronous control is used in time-interleaved converter, then the control is simple, but the processing efficiency is limited by fixed timing
Solution Approach 1:
The patent implements an asynchronous control mechanism that dynamically adjusts the timing of fine conversion based on the actual completion status of coarse conversion. The control circuit monitors the status signals from the first capacitor array circuit and selectively advances the start time of the second capacitor array circuit's noise shaping conversion, optimizing processing efficiency without requiring complex predetermined timing schedules.
Solution Approach 2:
The control circuit automatically adjusts the timing coordination between parallel conversion channels based on their own operational status. The first capacitor array circuit's completion status directly controls the start timing of the second capacitor array circuit, creating a self-regulating system that maximizes processing efficiency without external intervention or complex centralized timing control.
Data Source
AI summary
A time-interleaved analog to digital converter includes first and second capacitor array circuits, first and second transfer circuits, a fine converter circuitry, and an encoder circuit. The capacitor array circuits sample an input signal and generate first residues according to first quantization signals. The first and second transfer circuits transfer first and second residues respectively. The fine converter circuitry performs a noise shaping signal conversion on the first and second residues to generate a second quantization signal. A turn-on time of the corresponding first transfer circuit is determined based on the coarse conversion corresponding to a first capacitor array circuit and the noise shaping signal conversion corresponding to a second capacitor array circuit to selectively bring forward a start time of the noise shaping signal conversion. The encoder circuit generates a digital output according to the first and the second quantization signals.